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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Make sure that element no.1 extracted from <2 x i1> translates to extracting4; bit no.4 from the predicate register.5 6; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2)7; CHECK: r[[R0:[0-9]+]] = p[[P0]]8; This is what we're really testing: the bit index of 4.9; CHECK: p[[P0]] = tstbit(r[[R0]],#4)10 11define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 {12 %v0 = icmp eq <2 x i32> %a0, %a113 %v1 = extractelement <2 x i1> %v0, i32 114 %v2 = zext i1 %v1 to i3215 ret i32 %v216}17 18attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }19