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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Test that the compiler generates the correct code when sign-extending a4; predicate register when it is converted from one vector predicate type5; to another. In this case, the compiler generates two v4i1 EXTRACT_SUBVECT6; from a v8i1, for the lower and upper parts.7 8; CHECK: r[[REGH:([0-9]+)]]:[[REGL:([0-9]+)]] = mask(p{{[0-3]}})9; CHECK-DAG: = vsxtbh(r[[REGH]])10; CHECK-DAG: = vsxtbh(r[[REGL]])11 12target triple = "hexagon"13 14define void @f0(ptr %a0, ptr %a1) #0 {15b0:16 %v0 = load i16, ptr %a0, align 217 %v1 = sext i16 %v0 to i3218 %v2 = insertelement <8 x i32> undef, i32 %v1, i32 019 %v3 = shufflevector <8 x i32> %v2, <8 x i32> undef, <8 x i32> zeroinitializer20 %v4 = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>21 %v5 = and <8 x i32> %v4, %v322 %v6 = icmp ne <8 x i32> %v5, zeroinitializer23 %v7 = zext <8 x i1> %v6 to <8 x i16>24 store <8 x i16> %v7, ptr %a1, align 825 ret void26}27 28attributes #0 = { nounwind optsize "target-cpu"="hexagonv65" "target-features"="+hvx-length64b,+hvxv65,-long-calls" }29