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1# RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b \2# RUN: -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s3 4 5# Test that the operands are swapped for Add if the second operand6# is a qf32 to sf conversion. V6_vadd_qf32_mix supports first operand7# as qf32.8# CHECK-LABEL: name: qfpAddMix9# CHECK: %[[REG:([0-9]+)]]:hvxvr = V6_vmpy_qf32_sf10# CHECK: V6_vadd_qf32_mix %[[REG]]11 12---13name: qfpAddMix14tracksRegLiveness: true15 16body: |17 bb.0:18 liveins: $r0, $r1, $r2, $r319 %0:intregs = COPY $r020 %1:intregs = COPY $r121 %2:intregs = COPY $r222 %3:hvxvr = V6_vL32Ub_ai %0:intregs, 023 %4:hvxvr = V6_vL32Ub_ai %1:intregs, 024 %5:hvxvr = V6_vL32Ub_ai %2:intregs, 025 %6:hvxvr = V6_vmpy_qf32_sf %4, %526 %7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr27 %8:hvxvr = V6_vadd_sf %3:hvxvr, %7:hvxvr28...29 30 31# Test that we do not generate V6_vsub_qf32_mix for the below test.32# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf3233# is passed as second operand. As sub is not commutative, we should not34# generate the mix instruction.35# CHECK-LABEL: name: qfpSubNoMix36# CHECK-NOT: V6_vsub_qf32_mix37 38---39name: qfpSubNoMix40tracksRegLiveness: true41 42body: |43 bb.0:44 liveins: $r0, $r1, $r2, $r345 %0:intregs = COPY $r046 %1:intregs = COPY $r147 %2:intregs = COPY $r248 %3:hvxvr = V6_vL32Ub_ai %0:intregs, 049 %4:hvxvr = V6_vL32Ub_ai %1:intregs, 050 %5:hvxvr = V6_vL32Ub_ai %2:intregs, 051 %6:hvxvr = V6_vmpy_qf32_sf %4, %552 %7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr53 %8:hvxvr = V6_vsub_sf %3:hvxvr, %7:hvxvr54...55 56 57# Test that we do generate V6_vsub_qf32_mix for the below test.58# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf3259# is passed as first operand. So, V6_vsub_qf32_mix must be generated.60# CHECK-LABEL: name: qfpSubMix61# CHECK: V6_vsub_qf32_mix62 63---64name: qfpSubMix65tracksRegLiveness: true66 67body: |68 bb.0:69 liveins: $r0, $r1, $r2, $r370 %0:intregs = COPY $r071 %1:intregs = COPY $r172 %2:intregs = COPY $r273 %3:hvxvr = V6_vL32Ub_ai %0:intregs, 074 %4:hvxvr = V6_vL32Ub_ai %1:intregs, 075 %5:hvxvr = V6_vL32Ub_ai %2:intregs, 076 %6:hvxvr = V6_vmpy_qf32_sf %4, %577 %7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr78 %8:hvxvr = V6_vsub_sf %7:hvxvr, %3:hvxvr79...80