33 lines · plain
1; RUN: llc -march=hexagon < %s | FileCheck %s2; REQUIRES: hexagon3 4; This test was asserting because getVRegDef() was called on a register with5; multiple defs.6; Checks that the test does not assert and vsub is generated.7; CHECK: vsub8 9target triple = "hexagon"10 11@v = common dso_local local_unnamed_addr global <32 x i32> zeroinitializer, align 12812 13; Function Attrs: nounwind14define dso_local void @hvx_twoSum(<32 x i32>* nocapture noundef writeonly %s2lo) local_unnamed_addr #0 {15entry:16 %0 = load <32 x i32>, <32 x i32>* @v, align 12817 %call = tail call inreg <32 x i32> @MY_Vsf_equals_Vqf32(<32 x i32> noundef %0) #318 %1 = tail call <32 x i32> @llvm.hexagon.V6.vsub.sf.128B(<32 x i32> %call, <32 x i32> %call)19 store <32 x i32> %1, <32 x i32>* @v, align 12820 store <32 x i32> %1, <32 x i32>* %s2lo, align 12821 ret void22}23 24declare dso_local inreg <32 x i32> @MY_Vsf_equals_Vqf32(<32 x i32> noundef) local_unnamed_addr #125 26; Function Attrs: nofree nosync nounwind readnone27declare <32 x i32> @llvm.hexagon.V6.vsub.sf.128B(<32 x i32>, <32 x i32>) #228 29attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv73" "target-features"="+hvx-length128b,+hvxv73,+v73,-long-calls" }30attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv73" "target-features"="+hvx-length128b,+hvxv73,+v73,-long-calls" }31attributes #2 = { nofree nosync nounwind readnone }32attributes #3 = { nounwind }33