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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define <4 x i8> @f0(<4 x i8> %a0) unnamed_addr #0 {5; CHECK-LABEL: f0:6; CHECK: // %bb.0: // %b07; CHECK-NEXT: {8; CHECK-NEXT: r1:0 = vsxtbh(r0)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: r1:0 = vasrh(r1:0,#1)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: r0 = vtrunehb(r1:0)15; CHECK-NEXT: jumpr r3116; CHECK-NEXT: }17b0:18 %v0 = ashr <4 x i8> %a0, <i8 1, i8 1, i8 1, i8 1>19 ret <4 x i8> %v020}21 22define <4 x i8> @f1(<4 x i8> %a0) unnamed_addr #0 {23; CHECK-LABEL: f1:24; CHECK: // %bb.0: // %b025; CHECK-NEXT: {26; CHECK-NEXT: r1:0 = vzxtbh(r0)27; CHECK-NEXT: }28; CHECK-NEXT: {29; CHECK-NEXT: r1:0 = vlsrh(r1:0,#1)30; CHECK-NEXT: }31; CHECK-NEXT: {32; CHECK-NEXT: r0 = vtrunehb(r1:0)33; CHECK-NEXT: jumpr r3134; CHECK-NEXT: }35b0:36 %v0 = lshr <4 x i8> %a0, <i8 1, i8 1, i8 1, i8 1>37 ret <4 x i8> %v038}39 40define <4 x i8> @f2(<4 x i8> %a0) unnamed_addr #0 {41; CHECK-LABEL: f2:42; CHECK: // %bb.0: // %b043; CHECK-NEXT: {44; CHECK-NEXT: r1:0 = vzxtbh(r0)45; CHECK-NEXT: }46; CHECK-NEXT: {47; CHECK-NEXT: r1:0 = vaslh(r1:0,#1)48; CHECK-NEXT: }49; CHECK-NEXT: {50; CHECK-NEXT: r0 = vtrunehb(r1:0)51; CHECK-NEXT: jumpr r3152; CHECK-NEXT: }53b0:54 %v0 = shl <4 x i8> %a0, <i8 1, i8 1, i8 1, i8 1>55 ret <4 x i8> %v056}57 58 59define <8 x i8> @f3(<8 x i8> %a0) unnamed_addr #0 {60; CHECK-LABEL: f3:61; CHECK: // %bb.0: // %b062; CHECK-NEXT: {63; CHECK-NEXT: r3:2 = vsxtbh(r1)64; CHECK-NEXT: r5:4 = vsxtbh(r0)65; CHECK-NEXT: }66; CHECK-NEXT: {67; CHECK-NEXT: r1:0 = vasrh(r5:4,#1)68; CHECK-NEXT: r3:2 = vasrh(r3:2,#1)69; CHECK-NEXT: }70; CHECK-NEXT: {71; CHECK-NEXT: r0 = vtrunehb(r1:0)72; CHECK-NEXT: r1 = vtrunehb(r3:2)73; CHECK-NEXT: }74; CHECK-NEXT: {75; CHECK-NEXT: jumpr r3176; CHECK-NEXT: }77b0:78 %v0 = ashr <8 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>79 ret <8 x i8> %v080}81 82define <8 x i8> @f4(<8 x i8> %a0) unnamed_addr #0 {83; CHECK-LABEL: f4:84; CHECK: // %bb.0: // %b085; CHECK-NEXT: {86; CHECK-NEXT: r3:2 = vzxtbh(r1)87; CHECK-NEXT: r5:4 = vzxtbh(r0)88; CHECK-NEXT: }89; CHECK-NEXT: {90; CHECK-NEXT: r1:0 = vlsrh(r5:4,#1)91; CHECK-NEXT: r3:2 = vlsrh(r3:2,#1)92; CHECK-NEXT: }93; CHECK-NEXT: {94; CHECK-NEXT: r0 = vtrunehb(r1:0)95; CHECK-NEXT: r1 = vtrunehb(r3:2)96; CHECK-NEXT: }97; CHECK-NEXT: {98; CHECK-NEXT: jumpr r3199; CHECK-NEXT: }100b0:101 %v0 = lshr <8 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>102 ret <8 x i8> %v0103}104 105define <8 x i8> @f5(<8 x i8> %a0) unnamed_addr #0 {106; CHECK-LABEL: f5:107; CHECK: // %bb.0: // %b0108; CHECK-NEXT: {109; CHECK-NEXT: r3:2 = vzxtbh(r1)110; CHECK-NEXT: r5:4 = vzxtbh(r0)111; CHECK-NEXT: }112; CHECK-NEXT: {113; CHECK-NEXT: r1:0 = vaslh(r5:4,#1)114; CHECK-NEXT: r3:2 = vaslh(r3:2,#1)115; CHECK-NEXT: }116; CHECK-NEXT: {117; CHECK-NEXT: r0 = vtrunehb(r1:0)118; CHECK-NEXT: r1 = vtrunehb(r3:2)119; CHECK-NEXT: }120; CHECK-NEXT: {121; CHECK-NEXT: jumpr r31122; CHECK-NEXT: }123b0:124 %v0 = shl <8 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>125 ret <8 x i8> %v0126}127 128 129define <2 x i16> @f6(<2 x i16> %a0) unnamed_addr #0 {130; CHECK-LABEL: f6:131; CHECK: // %bb.0: // %b0132; CHECK-NEXT: {133; CHECK-NEXT: r1:0 = vasrh(r1:0,#1)134; CHECK-NEXT: jumpr r31135; CHECK-NEXT: }136b0:137 %v0 = ashr <2 x i16> %a0, <i16 1, i16 1>138 ret <2 x i16> %v0139}140 141define <2 x i16> @f7(<2 x i16> %a0) unnamed_addr #0 {142; CHECK-LABEL: f7:143; CHECK: // %bb.0: // %b0144; CHECK-NEXT: {145; CHECK-NEXT: r1:0 = vlsrh(r1:0,#1)146; CHECK-NEXT: jumpr r31147; CHECK-NEXT: }148b0:149 %v0 = lshr <2 x i16> %a0, <i16 1, i16 1>150 ret <2 x i16> %v0151}152 153define <2 x i16> @f8(<2 x i16> %a0) unnamed_addr #0 {154; CHECK-LABEL: f8:155; CHECK: // %bb.0: // %b0156; CHECK-NEXT: {157; CHECK-NEXT: r1:0 = vaslh(r1:0,#1)158; CHECK-NEXT: jumpr r31159; CHECK-NEXT: }160b0:161 %v0 = shl <2 x i16> %a0, <i16 1, i16 1>162 ret <2 x i16> %v0163}164 165 166define <4 x i16> @f9(<4 x i16> %a0) unnamed_addr #0 {167; CHECK-LABEL: f9:168; CHECK: // %bb.0: // %b0169; CHECK-NEXT: {170; CHECK-NEXT: r1:0 = vasrh(r1:0,#1)171; CHECK-NEXT: jumpr r31172; CHECK-NEXT: }173b0:174 %v0 = ashr <4 x i16> %a0, <i16 1, i16 1, i16 1, i16 1>175 ret <4 x i16> %v0176}177 178define <4 x i16> @f10(<4 x i16> %a0) unnamed_addr #0 {179; CHECK-LABEL: f10:180; CHECK: // %bb.0: // %b0181; CHECK-NEXT: {182; CHECK-NEXT: r1:0 = vlsrh(r1:0,#1)183; CHECK-NEXT: jumpr r31184; CHECK-NEXT: }185b0:186 %v0 = lshr <4 x i16> %a0, <i16 1, i16 1, i16 1, i16 1>187 ret <4 x i16> %v0188}189 190define <4 x i16> @f11(<4 x i16> %a0) unnamed_addr #0 {191; CHECK-LABEL: f11:192; CHECK: // %bb.0: // %b0193; CHECK-NEXT: {194; CHECK-NEXT: r1:0 = vaslh(r1:0,#1)195; CHECK-NEXT: jumpr r31196; CHECK-NEXT: }197b0:198 %v0 = shl <4 x i16> %a0, <i16 1, i16 1, i16 1, i16 1>199 ret <4 x i16> %v0200}201 202 203define <2 x i32> @f12(<2 x i32> %a0) unnamed_addr #0 {204; CHECK-LABEL: f12:205; CHECK: // %bb.0: // %b0206; CHECK-NEXT: {207; CHECK-NEXT: r1:0 = vasrw(r1:0,#1)208; CHECK-NEXT: jumpr r31209; CHECK-NEXT: }210b0:211 %v0 = ashr <2 x i32> %a0, <i32 1, i32 1>212 ret <2 x i32> %v0213}214 215define <2 x i32> @f13(<2 x i32> %a0) unnamed_addr #0 {216; CHECK-LABEL: f13:217; CHECK: // %bb.0: // %b0218; CHECK-NEXT: {219; CHECK-NEXT: r1:0 = vlsrw(r1:0,#1)220; CHECK-NEXT: jumpr r31221; CHECK-NEXT: }222b0:223 %v0 = lshr <2 x i32> %a0, <i32 1, i32 1>224 ret <2 x i32> %v0225}226 227define <2 x i32> @f14(<2 x i32> %a0) unnamed_addr #0 {228; CHECK-LABEL: f14:229; CHECK: // %bb.0: // %b0230; CHECK-NEXT: {231; CHECK-NEXT: r1:0 = vaslw(r1:0,#1)232; CHECK-NEXT: jumpr r31233; CHECK-NEXT: }234b0:235 %v0 = shl <2 x i32> %a0, <i32 1, i32 1>236 ret <2 x i32> %v0237}238 239define <4 x i8> @f15(<4 x i8> %a0) unnamed_addr #0 {240; CHECK-LABEL: f15:241; CHECK: // %bb.0: // %b0242; CHECK-NEXT: {243; CHECK-NEXT: r1 = extract(r0,#8,#16)244; CHECK-NEXT: r2 = extract(r0,#8,#8)245; CHECK-NEXT: r3 = sxtb(r0)246; CHECK-NEXT: }247; CHECK-NEXT: {248; CHECK-NEXT: r4 = extract(r0,#8,#24)249; CHECK-NEXT: r2 = asl(r2,#6)250; CHECK-NEXT: }251; CHECK-NEXT: {252; CHECK-NEXT: r3 = extractu(r3,#8,#1)253; CHECK-NEXT: r0 = asl(r4,#4)254; CHECK-NEXT: }255; CHECK-NEXT: {256; CHECK-NEXT: r1 = extractu(r1,#8,#3)257; CHECK-NEXT: r2 = or(r3,and(r2,##65280))258; CHECK-NEXT: }259; CHECK-NEXT: {260; CHECK-NEXT: r0 = or(r1,and(r0,##65280))261; CHECK-NEXT: }262; CHECK-NEXT: {263; CHECK-NEXT: r0 = combine(r0.l,r2.l)264; CHECK-NEXT: jumpr r31265; CHECK-NEXT: }266b0:267 %v0 = ashr <4 x i8> %a0, <i8 1, i8 2, i8 3, i8 4>268 ret <4 x i8> %v0269}270 271define <4 x i8> @f16(<4 x i8> %a0) unnamed_addr #0 {272; CHECK-LABEL: f16:273; CHECK: // %bb.0: // %b0274; CHECK-NEXT: {275; CHECK-NEXT: r1 = extractu(r0,#8,#8)276; CHECK-NEXT: r2 = extractu(r0,#8,#24)277; CHECK-NEXT: }278; CHECK-NEXT: {279; CHECK-NEXT: r3 = extractu(r0,#7,#1)280; CHECK-NEXT: r4 = extractu(r0,#5,#19)281; CHECK-NEXT: r1 = and(r1,#252)282; CHECK-NEXT: r2 = and(r2,#240)283; CHECK-NEXT: }284; CHECK-NEXT: {285; CHECK-NEXT: r3 |= asl(r1,#6)286; CHECK-NEXT: r4 |= asl(r2,#4)287; CHECK-NEXT: }288; CHECK-NEXT: {289; CHECK-NEXT: r0 = combine(r4.l,r3.l)290; CHECK-NEXT: jumpr r31291; CHECK-NEXT: }292b0:293 %v0 = lshr <4 x i8> %a0, <i8 1, i8 2, i8 3, i8 4>294 ret <4 x i8> %v0295}296 297define <4 x i8> @f17(<4 x i8> %a0) unnamed_addr #0 {298; CHECK-LABEL: f17:299; CHECK: // %bb.0: // %b0300; CHECK-NEXT: {301; CHECK-NEXT: r1 = extractu(r0,#8,#16)302; CHECK-NEXT: r2 = extractu(r0,#8,#8)303; CHECK-NEXT: }304; CHECK-NEXT: {305; CHECK-NEXT: r3 = extractu(r0,#8,#24)306; CHECK-NEXT: r1 = and(#248,asl(r1,#3))307; CHECK-NEXT: }308; CHECK-NEXT: {309; CHECK-NEXT: r0 = and(#254,asl(r0,#1))310; CHECK-NEXT: r1 = insert(r3,#4,#12)311; CHECK-NEXT: }312; CHECK-NEXT: {313; CHECK-NEXT: r0 = insert(r2,#6,#10)314; CHECK-NEXT: }315; CHECK-NEXT: {316; CHECK-NEXT: r0 = combine(r1.l,r0.l)317; CHECK-NEXT: jumpr r31318; CHECK-NEXT: }319b0:320 %v0 = shl <4 x i8> %a0, <i8 1, i8 2, i8 3, i8 4>321 ret <4 x i8> %v0322}323 324define <8 x i8> @f18(<8 x i8> %a0) unnamed_addr #0 {325; CHECK-LABEL: f18:326; CHECK: // %bb.0: // %b0327; CHECK-NEXT: {328; CHECK-NEXT: r3:2 = extractu(r1:0,#8,#48)329; CHECK-NEXT: r5:4 = extractu(r1:0,#8,#24)330; CHECK-NEXT: }331; CHECK-NEXT: {332; CHECK-NEXT: r7:6 = extractu(r1:0,#8,#16)333; CHECK-NEXT: r5 = extract(r0,#8,#8)334; CHECK-NEXT: r3 = sxtb(r0)335; CHECK-NEXT: r2 = sxtb(r2)336; CHECK-NEXT: }337; CHECK-NEXT: {338; CHECK-NEXT: r7 = extract(r1,#8,#8)339; CHECK-NEXT: r9:8 = extractu(r1:0,#8,#32)340; CHECK-NEXT: }341; CHECK-NEXT: {342; CHECK-NEXT: r1:0 = extractu(r1:0,#8,#56)343; CHECK-NEXT: r3 = extractu(r3,#8,#1)344; CHECK-NEXT: }345; CHECK-NEXT: {346; CHECK-NEXT: r5 = asl(r5,#6)347; CHECK-NEXT: r6 = sxtb(r8)348; CHECK-NEXT: r1 = sxtb(r4)349; CHECK-NEXT: r4 = sxtb(r6)350; CHECK-NEXT: }351; CHECK-NEXT: {352; CHECK-NEXT: r5 = or(r3,and(r5,##65280))353; CHECK-NEXT: r3 = asl(r7,#5)354; CHECK-NEXT: r0 = sxtb(r0)355; CHECK-NEXT: }356; CHECK-NEXT: {357; CHECK-NEXT: r6 = extractu(r6,#8,#2)358; CHECK-NEXT: r1 = asl(r1,#4)359; CHECK-NEXT: }360; CHECK-NEXT: {361; CHECK-NEXT: r4 = extractu(r4,#8,#3)362; CHECK-NEXT: r7 = asl(r0,#7)363; CHECK-NEXT: }364; CHECK-NEXT: {365; CHECK-NEXT: r2 = extractu(r2,#8,#4)366; CHECK-NEXT: r1 = or(r4,and(r1,##65280))367; CHECK-NEXT: }368; CHECK-NEXT: {369; CHECK-NEXT: r3 = or(r6,and(r3,##65280))370; CHECK-NEXT: r7 = or(r2,and(r7,##65280))371; CHECK-NEXT: }372; CHECK-NEXT: {373; CHECK-NEXT: r0 = combine(r1.l,r5.l)374; CHECK-NEXT: jumpr r31375; CHECK-NEXT: r1 = combine(r7.l,r3.l)376; CHECK-NEXT: }377b0:378 %v0 = ashr <8 x i8> %a0, <i8 1, i8 2, i8 3, i8 4, i8 2, i8 3, i8 4, i8 1>379 ret <8 x i8> %v0380}381 382define <8 x i8> @f19(<8 x i8> %a0) unnamed_addr #0 {383; CHECK-LABEL: f19:384; CHECK: // %bb.0: // %b0385; CHECK-NEXT: {386; CHECK-NEXT: r3:2 = extractu(r1:0,#8,#8)387; CHECK-NEXT: r5:4 = extractu(r1:0,#8,#24)388; CHECK-NEXT: }389; CHECK-NEXT: {390; CHECK-NEXT: r3 = extractu(r1,#4,#20)391; CHECK-NEXT: r5 = extractu(r0,#7,#1)392; CHECK-NEXT: r2 = and(r2,#252)393; CHECK-NEXT: r4 = and(r4,#240)394; CHECK-NEXT: }395; CHECK-NEXT: {396; CHECK-NEXT: r6 = extractu(r0,#5,#19)397; CHECK-NEXT: r9:8 = extractu(r1:0,#8,#40)398; CHECK-NEXT: }399; CHECK-NEXT: {400; CHECK-NEXT: r7 = extractu(r1,#6,#2)401; CHECK-NEXT: r1:0 = extractu(r1:0,#8,#56)402; CHECK-NEXT: }403; CHECK-NEXT: {404; CHECK-NEXT: r5 |= asl(r2,#6)405; CHECK-NEXT: r6 |= asl(r4,#4)406; CHECK-NEXT: r1 = and(r8,#248)407; CHECK-NEXT: r11 = and(r0,#254)408; CHECK-NEXT: }409; CHECK-NEXT: {410; CHECK-NEXT: r7 |= asl(r1,#5)411; CHECK-NEXT: r3 |= asl(r11,#7)412; CHECK-NEXT: r0 = combine(r6.l,r5.l)413; CHECK-NEXT: }414; CHECK-NEXT: {415; CHECK-NEXT: r1 = combine(r3.l,r7.l)416; CHECK-NEXT: jumpr r31417; CHECK-NEXT: }418b0:419 %v0 = lshr <8 x i8> %a0, <i8 1, i8 2, i8 3, i8 4, i8 2, i8 3, i8 4, i8 1>420 ret <8 x i8> %v0421}422 423define <8 x i8> @f20(<8 x i8> %a0) unnamed_addr #0 {424; CHECK-LABEL: f20:425; CHECK: // %bb.0: // %b0426; CHECK-NEXT: {427; CHECK-NEXT: r5:4 = extractu(r1:0,#8,#16)428; CHECK-NEXT: r3:2 = extractu(r1:0,#8,#48)429; CHECK-NEXT: }430; CHECK-NEXT: {431; CHECK-NEXT: r4 = and(#248,asl(r4,#3))432; CHECK-NEXT: r15:14 = extractu(r1:0,#8,#32)433; CHECK-NEXT: r5 = r0434; CHECK-NEXT: }435; CHECK-NEXT: {436; CHECK-NEXT: r13:12 = extractu(r1:0,#8,#24)437; CHECK-NEXT: r7:6 = extractu(r1:0,#8,#56)438; CHECK-NEXT: r3 = r4439; CHECK-NEXT: }440; CHECK-NEXT: {441; CHECK-NEXT: r2 = and(#240,asl(r2,#4))442; CHECK-NEXT: r9:8 = extractu(r1:0,#8,#8)443; CHECK-NEXT: }444; CHECK-NEXT: {445; CHECK-NEXT: r5 = and(#254,asl(r5,#1))446; CHECK-NEXT: r4 = insert(r14,#6,#2)447; CHECK-NEXT: }448; CHECK-NEXT: {449; CHECK-NEXT: r1:0 = extractu(r1:0,#8,#40)450; CHECK-NEXT: r3 = insert(r12,#4,#12)451; CHECK-NEXT: }452; CHECK-NEXT: {453; CHECK-NEXT: r5 = insert(r8,#6,#10)454; CHECK-NEXT: r4 = insert(r0,#5,#11)455; CHECK-NEXT: }456; CHECK-NEXT: {457; CHECK-NEXT: r2 = insert(r6,#7,#9)458; CHECK-NEXT: r0 = combine(r3.l,r5.l)459; CHECK-NEXT: }460; CHECK-NEXT: {461; CHECK-NEXT: r1 = combine(r2.l,r4.l)462; CHECK-NEXT: jumpr r31463; CHECK-NEXT: }464b0:465 %v0 = shl <8 x i8> %a0, <i8 1, i8 2, i8 3, i8 4, i8 2, i8 3, i8 4, i8 1>466 ret <8 x i8> %v0467}468 469define <2 x i16> @f21(<2 x i16> %a0) unnamed_addr #0 {470; CHECK-LABEL: f21:471; CHECK: // %bb.0: // %b0472; CHECK-NEXT: {473; CHECK-NEXT: r1 = extract(r0,#16,#16)474; CHECK-NEXT: r2 = extract(r0,#15,#1)475; CHECK-NEXT: }476; CHECK-NEXT: {477; CHECK-NEXT: r1 = asr(r1,#2)478; CHECK-NEXT: }479; CHECK-NEXT: {480; CHECK-NEXT: r0 = combine(r1.l,r2.l)481; CHECK-NEXT: jumpr r31482; CHECK-NEXT: }483b0:484 %v0 = ashr <2 x i16> %a0, <i16 1, i16 2>485 ret <2 x i16> %v0486}487 488define <2 x i16> @f22(<2 x i16> %a0) unnamed_addr #0 {489; CHECK-LABEL: f22:490; CHECK: // %bb.0: // %b0491; CHECK-NEXT: {492; CHECK-NEXT: r1 = extractu(r0,#16,#16)493; CHECK-NEXT: r2 = extractu(r0,#15,#1)494; CHECK-NEXT: }495; CHECK-NEXT: {496; CHECK-NEXT: r1 = extractu(r1,#14,#2)497; CHECK-NEXT: }498; CHECK-NEXT: {499; CHECK-NEXT: r0 = combine(r1.l,r2.l)500; CHECK-NEXT: jumpr r31501; CHECK-NEXT: }502b0:503 %v0 = lshr <2 x i16> %a0, <i16 1, i16 2>504 ret <2 x i16> %v0505}506 507define <2 x i16> @f23(<2 x i16> %a0) unnamed_addr #0 {508; CHECK-LABEL: f23:509; CHECK: // %bb.0: // %b0510; CHECK-NEXT: {511; CHECK-NEXT: r1:0 = bitsplit(r0,#16)512; CHECK-NEXT: }513; CHECK-NEXT: {514; CHECK-NEXT: r0 = asl(r0,#1)515; CHECK-NEXT: r1 = asl(r1,#2)516; CHECK-NEXT: }517; CHECK-NEXT: {518; CHECK-NEXT: r0 = combine(r1.l,r0.l)519; CHECK-NEXT: jumpr r31520; CHECK-NEXT: }521b0:522 %v0 = shl <2 x i16> %a0, <i16 1, i16 2>523 ret <2 x i16> %v0524}525 526define <4 x i16> @f24(<4 x i16> %a0) unnamed_addr #0 {527; CHECK-LABEL: f24:528; CHECK: // %bb.0: // %b0529; CHECK-NEXT: {530; CHECK-NEXT: r3:2 = extractu(r1:0,#16,#16)531; CHECK-NEXT: r5:4 = extractu(r1:0,#16,#48)532; CHECK-NEXT: }533; CHECK-NEXT: {534; CHECK-NEXT: r3 = extract(r0,#15,#1)535; CHECK-NEXT: r1 = extract(r1,#13,#3)536; CHECK-NEXT: r2 = sxth(r2)537; CHECK-NEXT: }538; CHECK-NEXT: {539; CHECK-NEXT: r4 = extract(r4,#12,#4)540; CHECK-NEXT: r0 = asr(r2,#2)541; CHECK-NEXT: }542; CHECK-NEXT: {543; CHECK-NEXT: r0 = combine(r0.l,r3.l)544; CHECK-NEXT: jumpr r31545; CHECK-NEXT: r1 = combine(r4.l,r1.l)546; CHECK-NEXT: }547b0:548 %v0 = ashr <4 x i16> %a0, <i16 1, i16 2, i16 3, i16 4>549 ret <4 x i16> %v0550}551 552define <4 x i16> @f25(<4 x i16> %a0) unnamed_addr #0 {553; CHECK-LABEL: f25:554; CHECK: // %bb.0: // %b0555; CHECK-NEXT: {556; CHECK-NEXT: r3:2 = extractu(r1:0,#16,#48)557; CHECK-NEXT: r5:4 = extractu(r1:0,#16,#16)558; CHECK-NEXT: }559; CHECK-NEXT: {560; CHECK-NEXT: r3 = extractu(r0,#15,#1)561; CHECK-NEXT: r0 = extractu(r4,#14,#2)562; CHECK-NEXT: }563; CHECK-NEXT: {564; CHECK-NEXT: r1 = extractu(r1,#13,#3)565; CHECK-NEXT: r2 = extractu(r2,#12,#4)566; CHECK-NEXT: r0 = combine(r0.l,r3.l)567; CHECK-NEXT: }568; CHECK-NEXT: {569; CHECK-NEXT: r1 = combine(r2.l,r1.l)570; CHECK-NEXT: jumpr r31571; CHECK-NEXT: }572b0:573 %v0 = lshr <4 x i16> %a0, <i16 1, i16 2, i16 3, i16 4>574 ret <4 x i16> %v0575}576 577define <4 x i16> @f26(<4 x i16> %a0) unnamed_addr #0 {578; CHECK-LABEL: f26:579; CHECK: // %bb.0: // %b0580; CHECK-NEXT: {581; CHECK-NEXT: r3:2 = extractu(r1:0,#16,#48)582; CHECK-NEXT: r5:4 = extractu(r1:0,#16,#16)583; CHECK-NEXT: }584; CHECK-NEXT: {585; CHECK-NEXT: r1:0 = extractu(r1:0,#16,#32)586; CHECK-NEXT: r4 = asl(r4,#2)587; CHECK-NEXT: r3 = zxth(r0)588; CHECK-NEXT: }589; CHECK-NEXT: {590; CHECK-NEXT: r1 = asl(r3,#1)591; CHECK-NEXT: r5 = asl(r0,#3)592; CHECK-NEXT: }593; CHECK-NEXT: {594; CHECK-NEXT: r2 = asl(r2,#4)595; CHECK-NEXT: r0 = combine(r4.l,r1.l)596; CHECK-NEXT: }597; CHECK-NEXT: {598; CHECK-NEXT: r1 = combine(r2.l,r5.l)599; CHECK-NEXT: jumpr r31600; CHECK-NEXT: }601b0:602 %v0 = shl <4 x i16> %a0, <i16 1, i16 2, i16 3, i16 4>603 ret <4 x i16> %v0604}605 606define <2 x i32> @f27(<2 x i32> %a0) unnamed_addr #0 {607; CHECK-LABEL: f27:608; CHECK: // %bb.0: // %b0609; CHECK-NEXT: {610; CHECK-NEXT: r0 = asr(r0,#1)611; CHECK-NEXT: r1 = asr(r1,#2)612; CHECK-NEXT: }613; CHECK-NEXT: {614; CHECK-NEXT: jumpr r31615; CHECK-NEXT: }616b0:617 %v0 = ashr <2 x i32> %a0, <i32 1, i32 2>618 ret <2 x i32> %v0619}620 621define <2 x i32> @f28(<2 x i32> %a0) unnamed_addr #0 {622; CHECK-LABEL: f28:623; CHECK: // %bb.0: // %b0624; CHECK-NEXT: {625; CHECK-NEXT: r0 = lsr(r0,#1)626; CHECK-NEXT: r1 = lsr(r1,#2)627; CHECK-NEXT: }628; CHECK-NEXT: {629; CHECK-NEXT: jumpr r31630; CHECK-NEXT: }631b0:632 %v0 = lshr <2 x i32> %a0, <i32 1, i32 2>633 ret <2 x i32> %v0634}635 636define <2 x i32> @f29(<2 x i32> %a0) unnamed_addr #0 {637; CHECK-LABEL: f29:638; CHECK: // %bb.0: // %b0639; CHECK-NEXT: {640; CHECK-NEXT: r0 = asl(r0,#1)641; CHECK-NEXT: r1 = asl(r1,#2)642; CHECK-NEXT: }643; CHECK-NEXT: {644; CHECK-NEXT: jumpr r31645; CHECK-NEXT: }646b0:647 %v0 = shl <2 x i32> %a0, <i32 1, i32 2>648 ret <2 x i32> %v0649}650 651attributes #0 = { nounwind }652