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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s3 4target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"5target triple = "hexagon"6 7; Check that store is post-incremented.8define void @foo(ptr nocapture %buf, ptr nocapture %dest, i32 %offset, i32 %oddBlock, i32 %gb) #0 {9; CHECK-LABEL: foo:10; CHECK: // %bb.0: // %entry11; CHECK-NEXT: {12; CHECK-NEXT: r2 = sub(r2,r3)13; CHECK-NEXT: r3 = sub(#31,r4)14; CHECK-NEXT: p0 = cmp.eq(r3,#0)15; CHECK-NEXT: r5 = memw(r0+#0)16; CHECK-NEXT: }17; CHECK-NEXT: {18; CHECK-NEXT: r5 = asr(r5,r4)19; CHECK-NEXT: r29 = add(r29,#-24)20; CHECK-NEXT: r9:8 = combine(#-1,#-1)21; CHECK-NEXT: memw(r0+#0) = r5.new22; CHECK-NEXT: }23; CHECK-NEXT: {24; CHECK-NEXT: r5 = and(r2,#7)25; CHECK-NEXT: r2 = r326; CHECK-NEXT: memd(r29+#8) = r19:1827; CHECK-NEXT: memd(r29+#16) = r17:1628; CHECK-NEXT: } // 8-byte Folded Spill29; CHECK-NEXT: {30; CHECK-NEXT: r7:6 = vaslw(r3:2,#1)31; CHECK-NEXT: if (p0) r5 = add(r5,#1)32; CHECK-NEXT: memd(r29+#0) = r21:2033; CHECK-NEXT: } // 8-byte Folded Spill34; CHECK-NEXT: {35; CHECK-NEXT: r0 = addasl(r1,r5,#2)36; CHECK-NEXT: r7:6 = vaddw(r7:6,r9:8)37; CHECK-NEXT: r14 = memw(r1+r5<<#2)38; CHECK-NEXT: }39; CHECK-NEXT: {40; CHECK-NEXT: r15 = memw(r0+#256)41; CHECK-NEXT: r10 = memw(r0+#512)42; CHECK-NEXT: }43; CHECK-NEXT: {44; CHECK-NEXT: r9:8 = vasrw(r15:14,#31)45; CHECK-NEXT: r19:18 = vasrw(r15:14,r3)46; CHECK-NEXT: r12 = memw(r0+#1024)47; CHECK-NEXT: }48; CHECK-NEXT: {49; CHECK-NEXT: p0 = vcmpw.eq(r9:8,r19:18)50; CHECK-NEXT: r17:16 = xor(r9:8,r7:6)51; CHECK-NEXT: r11 = memw(r0+#768)52; CHECK-NEXT: }53; CHECK-NEXT: {54; CHECK-NEXT: r15:14 = vmux(p0,r15:14,r17:16)55; CHECK-NEXT: r19:18 = vasrw(r11:10,#31)56; CHECK-NEXT: r13 = memw(r0+#1280)57; CHECK-NEXT: }58; CHECK-NEXT: {59; CHECK-NEXT: r21:20 = vasrw(r11:10,r3)60; CHECK-NEXT: r15:14 = vaslw(r15:14,r4)61; CHECK-NEXT: r8 = memw(r0+#1536)62; CHECK-NEXT: }63; CHECK-NEXT: {64; CHECK-NEXT: p1 = vcmpw.eq(r19:18,r21:20)65; CHECK-NEXT: r19:18 = xor(r19:18,r7:6)66; CHECK-NEXT: r9 = memw(r0+#1792)67; CHECK-NEXT: }68; CHECK-NEXT: {69; CHECK-NEXT: r21:20 = vasrw(r13:12,#31)70; CHECK-NEXT: r11:10 = vmux(p1,r11:10,r19:18)71; CHECK-NEXT: memw(r0+#32) = r1472; CHECK-NEXT: }73; CHECK-NEXT: {74; CHECK-NEXT: r17:16 = vasrw(r13:12,r3)75; CHECK-NEXT: r11:10 = vaslw(r11:10,r4)76; CHECK-NEXT: r14 = memw(r0+#2048)77; CHECK-NEXT: memw(r1+r5<<#2) = r1478; CHECK-NEXT: }79; CHECK-NEXT: {80; CHECK-NEXT: p0 = vcmpw.eq(r21:20,r17:16)81; CHECK-NEXT: r19:18 = xor(r21:20,r7:6)82; CHECK-NEXT: memw(r0+#288) = r1583; CHECK-NEXT: memw(r0+#256) = r1584; CHECK-NEXT: }85; CHECK-NEXT: {86; CHECK-NEXT: r17:16 = vasrw(r9:8,#31)87; CHECK-NEXT: r19:18 = vmux(p0,r13:12,r19:18)88; CHECK-NEXT: r15 = memw(r0+#2304)89; CHECK-NEXT: memw(r0+#544) = r1090; CHECK-NEXT: }91; CHECK-NEXT: {92; CHECK-NEXT: r21:20 = vasrw(r9:8,r3)93; CHECK-NEXT: memw(r0+#800) = r1194; CHECK-NEXT: memw(r0+#512) = r1095; CHECK-NEXT: }96; CHECK-NEXT: {97; CHECK-NEXT: r13:12 = vasrw(r15:14,#31)98; CHECK-NEXT: r11:10 = vasrw(r15:14,r3)99; CHECK-NEXT: memw(r0+#768) = r11100; CHECK-NEXT: }101; CHECK-NEXT: {102; CHECK-NEXT: p0 = vcmpw.eq(r17:16,r21:20)103; CHECK-NEXT: p1 = vcmpw.eq(r13:12,r11:10)104; CHECK-NEXT: }105; CHECK-NEXT: {106; CHECK-NEXT: r21:20 = xor(r13:12,r7:6)107; CHECK-NEXT: r17:16 = xor(r17:16,r7:6)108; CHECK-NEXT: r12 = memw(r0+#2560)109; CHECK-NEXT: r13 = memw(r0+#2816)110; CHECK-NEXT: }111; CHECK-NEXT: {112; CHECK-NEXT: r11:10 = vaslw(r19:18,r4)113; CHECK-NEXT: r17:16 = vmux(p0,r9:8,r17:16)114; CHECK-NEXT: }115; CHECK-NEXT: {116; CHECK-NEXT: r9:8 = vmux(p1,r15:14,r21:20)117; CHECK-NEXT: r19:18 = vasrw(r13:12,#31)118; CHECK-NEXT: r14 = memw(r0+#3072)119; CHECK-NEXT: memw(r0+#1056) = r10120; CHECK-NEXT: }121; CHECK-NEXT: {122; CHECK-NEXT: r21:20 = vasrw(r13:12,r3)123; CHECK-NEXT: r9:8 = vaslw(r9:8,r4)124; CHECK-NEXT: memw(r0+#1312) = r11125; CHECK-NEXT: memw(r0+#1024) = r10126; CHECK-NEXT: }127; CHECK-NEXT: {128; CHECK-NEXT: r11:10 = vaslw(r17:16,r4)129; CHECK-NEXT: p0 = vcmpw.eq(r19:18,r21:20)130; CHECK-NEXT: r15 = memw(r0+#3328)131; CHECK-NEXT: memw(r0+#1280) = r11132; CHECK-NEXT: }133; CHECK-NEXT: {134; CHECK-NEXT: r17:16 = xor(r19:18,r7:6)135; CHECK-NEXT: r21:20 = vasrw(r15:14,#31)136; CHECK-NEXT: memw(r0+#1568) = r10137; CHECK-NEXT: memw(r0+#1824) = r11138; CHECK-NEXT: }139; CHECK-NEXT: {140; CHECK-NEXT: r11:10 = vasrw(r15:14,r3)141; CHECK-NEXT: r13:12 = vmux(p0,r13:12,r17:16)142; CHECK-NEXT: memw(r0+#1536) = r10143; CHECK-NEXT: memw(r0+#1792) = r11144; CHECK-NEXT: }145; CHECK-NEXT: {146; CHECK-NEXT: p0 = vcmpw.eq(r21:20,r11:10)147; CHECK-NEXT: r19:18 = xor(r21:20,r7:6)148; CHECK-NEXT: r10 = memw(r0+#3584)149; CHECK-NEXT: memw(r0+#2080) = r8150; CHECK-NEXT: }151; CHECK-NEXT: {152; CHECK-NEXT: r19:18 = vmux(p0,r15:14,r19:18)153; CHECK-NEXT: r13:12 = vaslw(r13:12,r4)154; CHECK-NEXT: r11 = memw(r0+#3840)155; CHECK-NEXT: memw(r0+#2336) = r9156; CHECK-NEXT: }157; CHECK-NEXT: {158; CHECK-NEXT: r21:20 = vasrw(r11:10,#31)159; CHECK-NEXT: r3:2 = vasrw(r11:10,r3)160; CHECK-NEXT: memw(r0+#2048) = r8161; CHECK-NEXT: memw(r0+#2304) = r9162; CHECK-NEXT: }163; CHECK-NEXT: {164; CHECK-NEXT: r7:6 = xor(r21:20,r7:6)165; CHECK-NEXT: p0 = vcmpw.eq(r21:20,r3:2)166; CHECK-NEXT: r17:16 = memd(r29+#16)167; CHECK-NEXT: memw(r0+#2592) = r12168; CHECK-NEXT: } // 8-byte Folded Reload169; CHECK-NEXT: {170; CHECK-NEXT: r3:2 = vmux(p0,r11:10,r7:6)171; CHECK-NEXT: r9:8 = vaslw(r19:18,r4)172; CHECK-NEXT: r19:18 = memd(r29+#8)173; CHECK-NEXT: memw(r0+#2848) = r13174; CHECK-NEXT: } // 8-byte Folded Reload175; CHECK-NEXT: {176; CHECK-NEXT: r3:2 = vaslw(r3:2,r4)177; CHECK-NEXT: r29 = add(r29,#24)178; CHECK-NEXT: r21:20 = memd(r29+#0)179; CHECK-NEXT: memw(r0+#2560) = r12180; CHECK-NEXT: } // 8-byte Folded Reload181; CHECK-NEXT: {182; CHECK-NEXT: memw(r0+#2816) = r13183; CHECK-NEXT: memw(r0+#3104) = r8184; CHECK-NEXT: }185; CHECK-NEXT: {186; CHECK-NEXT: memw(r0+#3360) = r9187; CHECK-NEXT: memw(r0+#3072) = r8188; CHECK-NEXT: }189; CHECK-NEXT: {190; CHECK-NEXT: memw(r0+#3328) = r9191; CHECK-NEXT: memw(r0+#3616) = r2192; CHECK-NEXT: }193; CHECK-NEXT: {194; CHECK-NEXT: memw(r0+#3872) = r3195; CHECK-NEXT: memw(r0+#3584) = r2196; CHECK-NEXT: }197; CHECK-NEXT: {198; CHECK-NEXT: jumpr r31199; CHECK-NEXT: memw(r0+#3840) = r3200; CHECK-NEXT: }201entry:202 %0 = load i32, ptr %buf, align 4, !tbaa !0203 %shr = ashr i32 %0, %gb204 store i32 %shr, ptr %buf, align 4, !tbaa !0205 %not.tobool = icmp eq i32 %oddBlock, 0206 %1 = sub i32 %offset, %oddBlock207 %2 = zext i1 %not.tobool to i32208 %3 = and i32 %1, 7209 %4 = add i32 %2, %3210 %5 = add i32 %4, 8211 %p_sub8 = sub nsw i32 31, %gb212 %6 = insertelement <2 x i32> undef, i32 %p_sub8, i32 0213 %7 = insertelement <2 x i32> %6, i32 %p_sub8, i32 1214 %8 = bitcast <2 x i32> %7 to i64215 %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)216 %10 = bitcast i64 %9 to <2 x i32>217 %11 = tail call i64 @llvm.hexagon.A2.combinew(i32 -1, i32 -1)218 %12 = bitcast i64 %11 to <2 x i32>219 %sub12p_vec = add <2 x i32> %10, %12220 %p_22 = add i32 %4, 64221 %p_d.018 = getelementptr i32, ptr %dest, i32 %4222 %p_d.01823 = getelementptr i32, ptr %dest, i32 %p_22223 %p_25 = add i32 %4, 72224 %p_arrayidx14 = getelementptr i32, ptr %dest, i32 %5225 %p_arrayidx1426 = getelementptr i32, ptr %dest, i32 %p_25226 %_p_scalar_ = load i32, ptr %p_d.018, align 4227 %_p_vec_ = insertelement <2 x i32> undef, i32 %_p_scalar_, i32 0228 %_p_scalar_27 = load i32, ptr %p_d.01823, align 4229 %_p_vec_28 = insertelement <2 x i32> %_p_vec_, i32 %_p_scalar_27, i32 1230 %13 = bitcast <2 x i32> %_p_vec_28 to i64231 %14 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %13, i32 31)232 %15 = bitcast i64 %14 to <2 x i32>233 %shr9p_vec = ashr <2 x i32> %_p_vec_28, %7234 %xorp_vec = xor <2 x i32> %15, %sub12p_vec235 %16 = bitcast <2 x i32> %shr9p_vec to i64236 %17 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %14, i64 %16)237 %18 = bitcast <2 x i32> %xorp_vec to i64238 %19 = tail call i64 @llvm.hexagon.C2.vmux(i32 %17, i64 %13, i64 %18)239 %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)240 %21 = bitcast i64 %20 to <2 x i32>241 %22 = extractelement <2 x i32> %21, i32 0242 store i32 %22, ptr %p_arrayidx14, align 4243 %23 = extractelement <2 x i32> %21, i32 1244 store i32 %23, ptr %p_arrayidx1426, align 4245 store i32 %22, ptr %p_d.018, align 4246 store i32 %23, ptr %p_d.01823, align 4247 %p_21.1 = add i32 %4, 128248 %p_22.1 = add i32 %4, 192249 %p_d.018.1 = getelementptr i32, ptr %dest, i32 %p_21.1250 %p_d.01823.1 = getelementptr i32, ptr %dest, i32 %p_22.1251 %p_24.1 = add i32 %4, 136252 %p_25.1 = add i32 %4, 200253 %p_arrayidx14.1 = getelementptr i32, ptr %dest, i32 %p_24.1254 %p_arrayidx1426.1 = getelementptr i32, ptr %dest, i32 %p_25.1255 %_p_scalar_.1 = load i32, ptr %p_d.018.1, align 4256 %_p_vec_.1 = insertelement <2 x i32> undef, i32 %_p_scalar_.1, i32 0257 %_p_scalar_27.1 = load i32, ptr %p_d.01823.1, align 4258 %_p_vec_28.1 = insertelement <2 x i32> %_p_vec_.1, i32 %_p_scalar_27.1, i32 1259 %24 = bitcast <2 x i32> %_p_vec_28.1 to i64260 %25 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %24, i32 31)261 %26 = bitcast i64 %25 to <2 x i32>262 %shr9p_vec.1 = ashr <2 x i32> %_p_vec_28.1, %7263 %xorp_vec.1 = xor <2 x i32> %26, %sub12p_vec264 %27 = bitcast <2 x i32> %shr9p_vec.1 to i64265 %28 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %25, i64 %27)266 %29 = bitcast <2 x i32> %xorp_vec.1 to i64267 %30 = tail call i64 @llvm.hexagon.C2.vmux(i32 %28, i64 %24, i64 %29)268 %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb)269 %32 = bitcast i64 %31 to <2 x i32>270 %33 = extractelement <2 x i32> %32, i32 0271 store i32 %33, ptr %p_arrayidx14.1, align 4272 %34 = extractelement <2 x i32> %32, i32 1273 store i32 %34, ptr %p_arrayidx1426.1, align 4274 store i32 %33, ptr %p_d.018.1, align 4275 store i32 %34, ptr %p_d.01823.1, align 4276 %p_21.2 = add i32 %4, 256277 %p_22.2 = add i32 %4, 320278 %p_d.018.2 = getelementptr i32, ptr %dest, i32 %p_21.2279 %p_d.01823.2 = getelementptr i32, ptr %dest, i32 %p_22.2280 %p_24.2 = add i32 %4, 264281 %p_25.2 = add i32 %4, 328282 %p_arrayidx14.2 = getelementptr i32, ptr %dest, i32 %p_24.2283 %p_arrayidx1426.2 = getelementptr i32, ptr %dest, i32 %p_25.2284 %_p_scalar_.2 = load i32, ptr %p_d.018.2, align 4285 %_p_vec_.2 = insertelement <2 x i32> undef, i32 %_p_scalar_.2, i32 0286 %_p_scalar_27.2 = load i32, ptr %p_d.01823.2, align 4287 %_p_vec_28.2 = insertelement <2 x i32> %_p_vec_.2, i32 %_p_scalar_27.2, i32 1288 %35 = bitcast <2 x i32> %_p_vec_28.2 to i64289 %36 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %35, i32 31)290 %37 = bitcast i64 %36 to <2 x i32>291 %shr9p_vec.2 = ashr <2 x i32> %_p_vec_28.2, %7292 %xorp_vec.2 = xor <2 x i32> %37, %sub12p_vec293 %38 = bitcast <2 x i32> %shr9p_vec.2 to i64294 %39 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %36, i64 %38)295 %40 = bitcast <2 x i32> %xorp_vec.2 to i64296 %41 = tail call i64 @llvm.hexagon.C2.vmux(i32 %39, i64 %35, i64 %40)297 %42 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %41, i32 %gb)298 %43 = bitcast i64 %42 to <2 x i32>299 %44 = extractelement <2 x i32> %43, i32 0300 store i32 %44, ptr %p_arrayidx14.2, align 4301 %45 = extractelement <2 x i32> %43, i32 1302 store i32 %45, ptr %p_arrayidx1426.2, align 4303 store i32 %44, ptr %p_d.018.2, align 4304 store i32 %45, ptr %p_d.01823.2, align 4305 %p_21.3 = add i32 %4, 384306 %p_22.3 = add i32 %4, 448307 %p_d.018.3 = getelementptr i32, ptr %dest, i32 %p_21.3308 %p_d.01823.3 = getelementptr i32, ptr %dest, i32 %p_22.3309 %p_24.3 = add i32 %4, 392310 %p_25.3 = add i32 %4, 456311 %p_arrayidx14.3 = getelementptr i32, ptr %dest, i32 %p_24.3312 %p_arrayidx1426.3 = getelementptr i32, ptr %dest, i32 %p_25.3313 %_p_scalar_.3 = load i32, ptr %p_d.018.3, align 4314 %_p_vec_.3 = insertelement <2 x i32> undef, i32 %_p_scalar_.3, i32 0315 %_p_scalar_27.3 = load i32, ptr %p_d.01823.3, align 4316 %_p_vec_28.3 = insertelement <2 x i32> %_p_vec_.3, i32 %_p_scalar_27.3, i32 1317 %46 = bitcast <2 x i32> %_p_vec_28.3 to i64318 %47 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %46, i32 31)319 %48 = bitcast i64 %47 to <2 x i32>320 %shr9p_vec.3 = ashr <2 x i32> %_p_vec_28.3, %7321 %xorp_vec.3 = xor <2 x i32> %48, %sub12p_vec322 %49 = bitcast <2 x i32> %shr9p_vec.3 to i64323 %50 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %47, i64 %49)324 %51 = bitcast <2 x i32> %xorp_vec.3 to i64325 %52 = tail call i64 @llvm.hexagon.C2.vmux(i32 %50, i64 %46, i64 %51)326 %53 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %52, i32 %gb)327 %54 = bitcast i64 %53 to <2 x i32>328 %55 = extractelement <2 x i32> %54, i32 0329 store i32 %55, ptr %p_arrayidx14.3, align 4330 %56 = extractelement <2 x i32> %54, i32 1331 store i32 %56, ptr %p_arrayidx1426.3, align 4332 store i32 %55, ptr %p_d.018.3, align 4333 store i32 %56, ptr %p_d.01823.3, align 4334 %p_21.4 = add i32 %4, 512335 %p_22.4 = add i32 %4, 576336 %p_d.018.4 = getelementptr i32, ptr %dest, i32 %p_21.4337 %p_d.01823.4 = getelementptr i32, ptr %dest, i32 %p_22.4338 %p_24.4 = add i32 %4, 520339 %p_25.4 = add i32 %4, 584340 %p_arrayidx14.4 = getelementptr i32, ptr %dest, i32 %p_24.4341 %p_arrayidx1426.4 = getelementptr i32, ptr %dest, i32 %p_25.4342 %_p_scalar_.4 = load i32, ptr %p_d.018.4, align 4343 %_p_vec_.4 = insertelement <2 x i32> undef, i32 %_p_scalar_.4, i32 0344 %_p_scalar_27.4 = load i32, ptr %p_d.01823.4, align 4345 %_p_vec_28.4 = insertelement <2 x i32> %_p_vec_.4, i32 %_p_scalar_27.4, i32 1346 %57 = bitcast <2 x i32> %_p_vec_28.4 to i64347 %58 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %57, i32 31)348 %59 = bitcast i64 %58 to <2 x i32>349 %shr9p_vec.4 = ashr <2 x i32> %_p_vec_28.4, %7350 %xorp_vec.4 = xor <2 x i32> %59, %sub12p_vec351 %60 = bitcast <2 x i32> %shr9p_vec.4 to i64352 %61 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %58, i64 %60)353 %62 = bitcast <2 x i32> %xorp_vec.4 to i64354 %63 = tail call i64 @llvm.hexagon.C2.vmux(i32 %61, i64 %57, i64 %62)355 %64 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %63, i32 %gb)356 %65 = bitcast i64 %64 to <2 x i32>357 %66 = extractelement <2 x i32> %65, i32 0358 store i32 %66, ptr %p_arrayidx14.4, align 4359 %67 = extractelement <2 x i32> %65, i32 1360 store i32 %67, ptr %p_arrayidx1426.4, align 4361 store i32 %66, ptr %p_d.018.4, align 4362 store i32 %67, ptr %p_d.01823.4, align 4363 %p_21.5 = add i32 %4, 640364 %p_22.5 = add i32 %4, 704365 %p_d.018.5 = getelementptr i32, ptr %dest, i32 %p_21.5366 %p_d.01823.5 = getelementptr i32, ptr %dest, i32 %p_22.5367 %p_24.5 = add i32 %4, 648368 %p_25.5 = add i32 %4, 712369 %p_arrayidx14.5 = getelementptr i32, ptr %dest, i32 %p_24.5370 %p_arrayidx1426.5 = getelementptr i32, ptr %dest, i32 %p_25.5371 %_p_scalar_.5 = load i32, ptr %p_d.018.5, align 4372 %_p_vec_.5 = insertelement <2 x i32> undef, i32 %_p_scalar_.5, i32 0373 %_p_scalar_27.5 = load i32, ptr %p_d.01823.5, align 4374 %_p_vec_28.5 = insertelement <2 x i32> %_p_vec_.5, i32 %_p_scalar_27.5, i32 1375 %68 = bitcast <2 x i32> %_p_vec_28.5 to i64376 %69 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %68, i32 31)377 %70 = bitcast i64 %69 to <2 x i32>378 %shr9p_vec.5 = ashr <2 x i32> %_p_vec_28.5, %7379 %xorp_vec.5 = xor <2 x i32> %70, %sub12p_vec380 %71 = bitcast <2 x i32> %shr9p_vec.5 to i64381 %72 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %69, i64 %71)382 %73 = bitcast <2 x i32> %xorp_vec.5 to i64383 %74 = tail call i64 @llvm.hexagon.C2.vmux(i32 %72, i64 %68, i64 %73)384 %75 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %74, i32 %gb)385 %76 = bitcast i64 %75 to <2 x i32>386 %77 = extractelement <2 x i32> %76, i32 0387 store i32 %77, ptr %p_arrayidx14.5, align 4388 %78 = extractelement <2 x i32> %76, i32 1389 store i32 %78, ptr %p_arrayidx1426.5, align 4390 store i32 %77, ptr %p_d.018.5, align 4391 store i32 %78, ptr %p_d.01823.5, align 4392 %p_21.6 = add i32 %4, 768393 %p_22.6 = add i32 %4, 832394 %p_d.018.6 = getelementptr i32, ptr %dest, i32 %p_21.6395 %p_d.01823.6 = getelementptr i32, ptr %dest, i32 %p_22.6396 %p_24.6 = add i32 %4, 776397 %p_25.6 = add i32 %4, 840398 %p_arrayidx14.6 = getelementptr i32, ptr %dest, i32 %p_24.6399 %p_arrayidx1426.6 = getelementptr i32, ptr %dest, i32 %p_25.6400 %_p_scalar_.6 = load i32, ptr %p_d.018.6, align 4401 %_p_vec_.6 = insertelement <2 x i32> undef, i32 %_p_scalar_.6, i32 0402 %_p_scalar_27.6 = load i32, ptr %p_d.01823.6, align 4403 %_p_vec_28.6 = insertelement <2 x i32> %_p_vec_.6, i32 %_p_scalar_27.6, i32 1404 %79 = bitcast <2 x i32> %_p_vec_28.6 to i64405 %80 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %79, i32 31)406 %81 = bitcast i64 %80 to <2 x i32>407 %shr9p_vec.6 = ashr <2 x i32> %_p_vec_28.6, %7408 %xorp_vec.6 = xor <2 x i32> %81, %sub12p_vec409 %82 = bitcast <2 x i32> %shr9p_vec.6 to i64410 %83 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %80, i64 %82)411 %84 = bitcast <2 x i32> %xorp_vec.6 to i64412 %85 = tail call i64 @llvm.hexagon.C2.vmux(i32 %83, i64 %79, i64 %84)413 %86 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %85, i32 %gb)414 %87 = bitcast i64 %86 to <2 x i32>415 %88 = extractelement <2 x i32> %87, i32 0416 store i32 %88, ptr %p_arrayidx14.6, align 4417 %89 = extractelement <2 x i32> %87, i32 1418 store i32 %89, ptr %p_arrayidx1426.6, align 4419 store i32 %88, ptr %p_d.018.6, align 4420 store i32 %89, ptr %p_d.01823.6, align 4421 %p_21.7 = add i32 %4, 896422 %p_22.7 = add i32 %4, 960423 %p_d.018.7 = getelementptr i32, ptr %dest, i32 %p_21.7424 %p_d.01823.7 = getelementptr i32, ptr %dest, i32 %p_22.7425 %p_24.7 = add i32 %4, 904426 %p_25.7 = add i32 %4, 968427 %p_arrayidx14.7 = getelementptr i32, ptr %dest, i32 %p_24.7428 %p_arrayidx1426.7 = getelementptr i32, ptr %dest, i32 %p_25.7429 %_p_scalar_.7 = load i32, ptr %p_d.018.7, align 4430 %_p_vec_.7 = insertelement <2 x i32> undef, i32 %_p_scalar_.7, i32 0431 %_p_scalar_27.7 = load i32, ptr %p_d.01823.7, align 4432 %_p_vec_28.7 = insertelement <2 x i32> %_p_vec_.7, i32 %_p_scalar_27.7, i32 1433 %90 = bitcast <2 x i32> %_p_vec_28.7 to i64434 %91 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %90, i32 31)435 %92 = bitcast i64 %91 to <2 x i32>436 %shr9p_vec.7 = ashr <2 x i32> %_p_vec_28.7, %7437 %xorp_vec.7 = xor <2 x i32> %92, %sub12p_vec438 %93 = bitcast <2 x i32> %shr9p_vec.7 to i64439 %94 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %91, i64 %93)440 %95 = bitcast <2 x i32> %xorp_vec.7 to i64441 %96 = tail call i64 @llvm.hexagon.C2.vmux(i32 %94, i64 %90, i64 %95)442 %97 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %96, i32 %gb)443 %98 = bitcast i64 %97 to <2 x i32>444 %99 = extractelement <2 x i32> %98, i32 0445 store i32 %99, ptr %p_arrayidx14.7, align 4446 %100 = extractelement <2 x i32> %98, i32 1447 store i32 %100, ptr %p_arrayidx1426.7, align 4448 store i32 %99, ptr %p_d.018.7, align 4449 store i32 %100, ptr %p_d.01823.7, align 4450 ret void451}452 453declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1454 455declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1456 457declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1458 459declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64) #1460 461declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1462 463declare i64 @llvm.hexagon.S2.asl.r.vw(i64, i32) #1464 465attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }466attributes #1 = { nounwind readnone }467 468!0 = !{!"int", !1}469!1 = !{!"omnipotent char", !2}470!2 = !{!"Simple C/C++ TBAA"}471