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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s3 4; Check that this compiles successfully.5 6target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"7target triple = "hexagon"8 9define i32 @fred(ptr %a0, i32 %cond) #0 {10; CHECK-LABEL: fred:11; CHECK: // %bb.0: // %b012; CHECK-NEXT: {13; CHECK-NEXT: p0 = cmp.eq(r1,#5); if (!p0.new) jump:t .LBB0_214; CHECK-NEXT: }15; CHECK-NEXT: // %bb.1: // %b216; CHECK-NEXT: {17; CHECK-NEXT: r3:2 = combine(#0,#0)18; CHECK-NEXT: r1:0 = memd(r0+#0)19; CHECK-NEXT: }20; CHECK-NEXT: {21; CHECK-NEXT: p0 = vcmph.eq(r1:0,r3:2)22; CHECK-NEXT: }23; CHECK-NEXT: {24; CHECK-NEXT: r1:0 = mask(p0)25; CHECK-NEXT: }26; CHECK-NEXT: {27; CHECK-NEXT: r0 = and(r0,#1)28; CHECK-NEXT: }29; CHECK-NEXT: {30; CHECK-NEXT: p0 = cmp.eq(r0,#11)31; CHECK-NEXT: r0 = #132; CHECK-NEXT: }33; CHECK-NEXT: {34; CHECK-NEXT: if (p0) r0 = #035; CHECK-NEXT: jumpr r3136; CHECK-NEXT: }37; CHECK-NEXT: .LBB0_2: // %b1438; CHECK-NEXT: {39; CHECK-NEXT: r0 = #040; CHECK-NEXT: jumpr r3141; CHECK-NEXT: }42b0:43 switch i32 %cond, label %b14 [44 i32 5, label %b245 i32 3, label %b146 ]47 48b1: ; preds = %b049 br label %b1450 51b2: ; preds = %b052 %v2 = load <8 x i16>, ptr %a0, align 6453 %v3 = icmp eq <8 x i16> %v2, zeroinitializer54 %v4 = zext <8 x i1> %v3 to <8 x i16>55 %v5 = add <8 x i16> zeroinitializer, %v456 %v6 = add <8 x i16> %v5, zeroinitializer57 %v7 = add <8 x i16> %v6, zeroinitializer58 %v8 = extractelement <8 x i16> %v7, i32 059 %v9 = add i16 %v8, 060 %v10 = add i16 %v9, 061 %v11 = add i16 %v10, 062 %v12 = icmp eq i16 %v11, 1163 br i1 %v12, label %b14, label %b1364 65b13: ; preds = %b266 ret i32 167 68b14: ; preds = %b2, %b1, %b069 ret i32 070}71 72attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }73