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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; REQUIRES: asserts3; CHECK: f0:4 5target triple = "hexagon"6 7; Function Attrs: nounwind readonly8define void @f0(ptr nocapture %a0) #0 {9b0:10 %v0 = alloca [16 x i16], align 811 %v1 = load i16, ptr %a0, align 2, !tbaa !012 %v2 = getelementptr [16 x i16], ptr %v0, i32 0, i32 513 br label %b1214 15b1: ; preds = %b1116 %v3 = icmp slt i16 %v1, 4617 br i1 %v3, label %b3, label %b218 19b2: ; preds = %b120 br label %b521 22b3: ; preds = %b123 br label %b424 25b4: ; preds = %b4, %b326 %v4 = phi i32 [ %v6, %b4 ], [ 0, %b3 ]27 %v5 = getelementptr inbounds [16 x i16], ptr %v0, i32 0, i32 %v428 store i16 1, ptr %v5, align 2, !tbaa !029 %v6 = add nsw i32 %v4, 130 %v7 = icmp eq i32 %v6, 1631 br i1 %v7, label %b8, label %b432 33b5: ; preds = %b7, %b234 %v8 = phi i32 [ %v12, %b7 ], [ 0, %b2 ]35 %v9 = getelementptr inbounds [16 x i16], ptr %v0, i32 0, i32 %v836 %v10 = load i16, ptr %v9, align 2, !tbaa !037 %v11 = icmp slt i16 %v10, 1338 br i1 %v11, label %b6, label %b739 40b6: ; preds = %b541 store i16 1, ptr %v9, align 2, !tbaa !042 br label %b743 44b7: ; preds = %b6, %b545 %v12 = add nsw i32 %v8, 146 %v13 = icmp eq i32 %v12, 1647 br i1 %v13, label %b9, label %b548 49b8: ; preds = %b450 br label %b1051 52b9: ; preds = %b753 br label %b1054 55b10: ; preds = %b11, %b9, %b856 ret void57 58b11: ; preds = %b1259 %v14 = add <2 x i32> %v31, %v3260 %v15 = extractelement <2 x i32> %v14, i32 061 %v16 = extractelement <2 x i32> %v14, i32 162 %v17 = add i32 %v16, %v1563 %v18 = icmp eq i32 %v17, 164 br i1 %v18, label %b1, label %b1065 66b12: ; preds = %b12, %b067 %v19 = phi <2 x i32> [ zeroinitializer, %b0 ], [ %v31, %b12 ]68 %v20 = phi <2 x i32> [ zeroinitializer, %b0 ], [ %v32, %b12 ]69 %v21 = phi ptr [ %v2, %b0 ], [ %v35, %b12 ]70 %v22 = phi i32 [ 0, %b0 ], [ %v33, %b12 ]71 %v24 = load <4 x i16>, ptr %v21, align 272 %v25 = icmp sgt <4 x i16> %v24, <i16 11, i16 11, i16 11, i16 11>73 %v26 = zext <4 x i1> %v25 to <4 x i16>74 %v27 = shufflevector <4 x i16> %v26, <4 x i16> undef, <2 x i32> <i32 2, i32 3>75 %v28 = shufflevector <4 x i16> %v26, <4 x i16> undef, <2 x i32> <i32 0, i32 1>76 %v29 = zext <2 x i16> %v28 to <2 x i32>77 %v30 = zext <2 x i16> %v27 to <2 x i32>78 %v31 = add <2 x i32> %v19, %v2979 %v32 = add <2 x i32> %v20, %v3080 %v33 = add nsw i32 %v22, 481 %v34 = icmp slt i32 %v22, 482 %v35 = getelementptr i16, ptr %v21, i32 483 br i1 %v34, label %b12, label %b1184}85 86attributes #0 = { nounwind readonly "target-cpu"="hexagonv55" }87 88!0 = !{!1, !1, i64 0}89!1 = !{!"short", !2}90!2 = !{!"omnipotent char", !3}91!3 = !{!"Simple C/C++ TBAA"}92