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1; RUN: llc -mtriple=hexagon -enable-pipeliner -verify-machineinstrs < %s2; REQUIRES: asserts3 4; This test fails in the machine verifier because the verifier thinks the5; return register is undefined, and because there is a basic block that6; ends with an unconditional branch that is not marked as a barrier.7;8; Enabling SWP exposes these bugs because the live variable analysis is9; performed earlier than the process implicit def pass. This ordering10; causes the JMPR machine instruction to contain two R0 operands, one11; with an undef and one with a kill flag.12 13@g0 = common global i32 0, align 414 15; Function Attrs: nounwind16define i32 @f0(i32 %a0) #0 {17b0:18 %v0 = icmp eq i32 %a0, 019 br i1 %v0, label %b2, label %b120 21b1: ; preds = %b022 %v1 = tail call i32 @f1(i32 %a0) #023 br label %b324 25b2: ; preds = %b026 store i32 0, ptr @g0, align 427 br label %b328 29b3: ; preds = %b2, %b130 ret i32 undef31}32 33declare i32 @f1(...)34 35attributes #0 = { nounwind }36