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1; RUN: llc -mtriple=hexagon -O3 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE2; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s --check-prefix=CHECK-AMODE3 4; CHECK-NO-AMODE: [[REG1:(r[0-9]+)]] = add({{r[0-9]+}},#0)5 6; CHECK-NO-AMODE: [[REG2:(r[0-9]+)]] = add([[REG1]],#128)7; CHECK-NO-AMODE: [[REG3:(r[0-9]+)]] = add([[REG1]],#256)8; CHECK-NO-AMODE: [[REG4:(r[0-9]+)]] = add([[REG1]],#384)9; CHECK-NO-AMODE: [[REG5:(r[0-9]+)]] = add([[REG1]],#512)10; CHECK-NO-AMODE: [[REG6:(r[0-9]+)]] = add([[REG1]],#640)11; CHECK-NO-AMODE: vmem([[REG1]]+#0) = vtmp.new12; CHECK-NO-AMODE: vmem([[REG2]]+#0) = vtmp.new13; CHECK-NO-AMODE: vmem([[REG3]]+#0) = vtmp.new14; CHECK-NO-AMODE: vmem([[REG4]]+#0) = vtmp.new15; CHECK-NO-AMODE: vmem([[REG5]]+#0) = vtmp.new16; CHECK-NO-AMODE: vmem([[REG6]]+#0) = vtmp.new17 18; Since we added some extra code to modify the addi offsets and bring them into19; the range of load/store instructions, we cannot guarantee which registers20; would be preserved, but we know for sure that only one Addi should be present21; and the other one should be removed followed by vmems with non-zero offset22 23; CHECK-AMODE: [[REG1:(r[0-9]+)]] = add({{r[0-9]+}},#{{[0-9]+}})24; CHECK-AMODE-NOT: {{r[0-9]+}} = add([[REG1]],{{[0-9]+}})25; CHECK-AMODE: vmem([[REG1]]+#{{[0-9]}}) = vtmp.new26; CHECK-AMODE: vmem([[REG2:(r[0-9]+)]]+#{{-?[0-9]}}) = vtmp.new27; CHECK-AMODE: vmem([[REG2]]+#{{-?[1-9]}}) = vtmp.new28; CHECK-AMODE: vmem([[REG2]]+#{{-?[1-9]}}) = vtmp.new29; CHECK-AMODE: vmem([[REG2]]+#{{-?[1-9]}}) = vtmp.new30; CHECK-AMODE: vmem([[REG2]]+#{{-?[1-9]}}) = vtmp.new31 32target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"33target triple = "hexagon"34 35; Function Attrs: nounwind readnone36define dso_local void @contiguos_vgather_test(i32 %Rb, i32 %mu, i32 %nloops, <32 x i32> %Vv, <64 x i32> %Vvv, <32 x i32> %Qs) local_unnamed_addr #0 {37entry:38 %Vout1 = alloca <32 x i32>, align 12839 call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %Vout1) #240 %cmp23 = icmp sgt i32 %nloops, 041 br i1 %cmp23, label %for.body.lr.ph, label %for.cond.cleanup42 43for.body.lr.ph: ; preds = %entry44 %add.ptr = getelementptr inbounds <32 x i32>, ptr %Vout1, i32 145 %add.ptr1 = getelementptr inbounds <32 x i32>, ptr %Vout1, i32 246 %add.ptr2 = getelementptr inbounds <32 x i32>, ptr %Vout1, i32 347 %0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %Qs, i32 -1)48 %add.ptr3 = getelementptr inbounds <32 x i32>, ptr %Vout1, i32 449 %add.ptr4 = getelementptr inbounds <32 x i32>, ptr %Vout1, i32 550 br label %for.body51 52for.cond.cleanup: ; preds = %for.body, %entry53 call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %Vout1) #254 ret void55 56for.body: ; preds = %for.body, %for.body.lr.ph57 %i.024 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]58 call void @llvm.hexagon.V6.vgathermh.128B(ptr nonnull %Vout1, i32 %Rb, i32 %mu, <32 x i32> %Vv)59 call void @llvm.hexagon.V6.vgathermw.128B(ptr nonnull %add.ptr, i32 %Rb, i32 %mu, <32 x i32> %Vv)60 call void @llvm.hexagon.V6.vgathermhw.128B(ptr nonnull %add.ptr1, i32 %Rb, i32 %mu, <64 x i32> %Vvv)61 call void @llvm.hexagon.V6.vgathermhq.128B(ptr nonnull %add.ptr2, <128 x i1> %0, i32 %Rb, i32 %mu, <32 x i32> %Vv)62 call void @llvm.hexagon.V6.vgathermwq.128B(ptr nonnull %add.ptr3, <128 x i1> %0, i32 %Rb, i32 %mu, <32 x i32> %Vv)63 call void @llvm.hexagon.V6.vgathermhwq.128B(ptr nonnull %add.ptr4, <128 x i1> %0, i32 %Rb, i32 %mu, <64 x i32> %Vvv)64 %inc = add nuw nsw i32 %i.024, 165 %exitcond = icmp eq i32 %inc, %nloops66 br i1 %exitcond, label %for.cond.cleanup, label %for.body67}68 69; Function Attrs: argmemonly nounwind70declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #171 72; Function Attrs: argmemonly nounwind73declare void @llvm.hexagon.V6.vgathermh.128B(ptr, i32, i32, <32 x i32>) #174 75; Function Attrs: argmemonly nounwind76declare void @llvm.hexagon.V6.vgathermw.128B(ptr, i32, i32, <32 x i32>) #177 78; Function Attrs: argmemonly nounwind79declare void @llvm.hexagon.V6.vgathermhw.128B(ptr, i32, i32, <64 x i32>) #180 81; Function Attrs: argmemonly nounwind82declare void @llvm.hexagon.V6.vgathermhq.128B(ptr, <128 x i1>, i32, i32, <32 x i32>) #183 84; Function Attrs: argmemonly nounwind85declare void @llvm.hexagon.V6.vgathermwq.128B(ptr, <128 x i1>, i32, i32, <32 x i32>) #186 87; Function Attrs: argmemonly nounwind88declare void @llvm.hexagon.V6.vgathermhwq.128B(ptr, <128 x i1>, i32, i32, <64 x i32>) #189 90; Function Attrs: argmemonly nounwind91declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #192 93declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) #194 95attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv65" "target-features"="+hvx-length128b,+hvxv65,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }96attributes #1 = { argmemonly nounwind }97attributes #2 = { nounwind }98 99!llvm.module.flags = !{!0}100 101!0 = !{i32 1, !"wchar_size", i32 4}102