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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s2; CHECK: = vmem(r{{[0-9]+}}++#1)3 4target triple = "hexagon-unknown--elf"5 6declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #07declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #08declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #09declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #010declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #011declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #012declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #013 14define void @f0(ptr %a0, ptr %a1) #1 {15b0:16 br label %b117 18b1: ; preds = %b2, %b119 %v0 = phi <128 x i8> [ %v7, %b1 ], [ undef, %b0 ]20 %v1 = phi i32 [ %v19, %b1 ], [ 0, %b0 ]21 %v2 = add nsw i32 %v1, undef22 %v3 = shl i32 %v2, 723 %v4 = add nsw i32 %v3, 12824 %v5 = getelementptr inbounds i8, ptr %a0, i32 %v425 %v7 = load <128 x i8>, ptr %v5, align 12826 %v8 = bitcast <128 x i8> %v0 to <32 x i32>27 %v9 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %v8, i32 1)28 %v10 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %v9) #129 %v11 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v10) #130 %v12 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %v11, <64 x i32> undef) #131 %v13 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v12)32 %v14 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %v13) #133 %v15 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v14, <32 x i32> undef)34 %v16 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v15) #135 %v17 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v16) #136 %v18 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v17, <32 x i32> undef) #137 store <32 x i32> %v18, ptr %a1, align 12838 %v19 = add nuw nsw i32 %v1, 139 br label %b140}41 42declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #043 44attributes #0 = { nounwind readnone }45attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }46