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1; RUN: llc -mtriple=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s2 3@g0 = common global double 0.000000e+00, align 84@g1 = common global double 0.000000e+00, align 85 6; CHECK-LABEL: <f0>:7; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo8define double @f0(i32 %a0, i32 %a1) {9b0:10 %v0 = load double, ptr @g0, align 8, !tbaa !011 %v1 = fptosi double %v0 to i6412 %v2 = load double, ptr @g1, align 8, !tbaa !013 %v3 = fptosi double %v2 to i6414 %v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a0)15 %v5 = sitofp i64 %v4 to double16 ret double %v517}18 19; Function Attrs: nounwind readnone20declare i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64, i64, i32) #021 22; CHECK-LABEL: <f1>:23; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi24define double @f1(i32 %a0, i32 %a1) {25b0:26 %v0 = load double, ptr @g0, align 8, !tbaa !027 %v1 = fptosi double %v0 to i6428 %v2 = load double, ptr @g1, align 8, !tbaa !029 %v3 = fptosi double %v2 to i6430 %v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a1)31 %v5 = sitofp i64 %v4 to double32 ret double %v533}34 35; CHECK-LABEL: <f2>:36; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo37define double @f2(i32 %a0, i32 %a1) {38b0:39 %v0 = load double, ptr @g1, align 8, !tbaa !040 %v1 = fptosi double %v0 to i6441 %v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a0)42 %v3 = sitofp i64 %v2 to double43 ret double %v344}45 46; Function Attrs: nounwind readnone47declare i64 @llvm.hexagon.M2.vrcmpys.s1(i64, i32) #048 49; CHECK-LABEL: <f3>:50; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi51define double @f3(i32 %a0, i32 %a1) {52b0:53 %v0 = load double, ptr @g1, align 8, !tbaa !054 %v1 = fptosi double %v0 to i6455 %v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a1)56 %v3 = sitofp i64 %v2 to double57 ret double %v358}59 60; CHECK-LABEL: <f4>:61; CHECK: e9a4c2e0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:lo }62; CHECK: e9a4c2c0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:hi }63define void @f4() {64b0:65 call void asm sideeffect "r0=vrcmpys(r5:4,r2):<<1:rnd:sat", ""(), !srcloc !466 call void asm sideeffect "r0=vrcmpys(r5:4,r3):<<1:rnd:sat", ""(), !srcloc !567 ret void68}69 70attributes #0 = { nounwind readnone }71 72!0 = !{!1, !1, i64 0}73!1 = !{!"double", !2, i64 0}74!2 = !{!"omnipotent char", !3, i64 0}75!3 = !{!"Simple C/C++ TBAA"}76!4 = !{i32 25}77!5 = !{i32 71}78