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1; RUN: llc -mtriple=hexagon -mattr="+hvxv60,+hvx-length64b" < %s2; REQUIRES: asserts3 4target triple = "hexagon"5 6; Function Attrs: nounwind7define void @fred() #0 {8entry:9 br label %for.body9.us10 11for.body9.us:12 %cmp10.us = icmp eq i32 0, undef13 %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef14 %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)15 %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> undef, <16 x i32> undef, <16 x i32> %0)16 %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)17 %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)18 %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)19 store <16 x i32> %4, ptr undef, align 6420 br i1 undef, label %for.body9.us, label %for.body43.us.preheader21 22for.body43.us.preheader: ; preds = %for.body9.us23 ret void24}25 26declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #127declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #128declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #129declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #130declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #131 32attributes #0 = { nounwind }33attributes #1 = { nounwind readnone }34