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1; Check the memd loads are generated by HexagonLoadStoreWidening pass2; Check that memw loads from adjacent memory location are replaced with memd,3; though the load/stores alias with instructions that occur later in the block.4; The order of memory operations remains unchanged.5 6; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s7 8target triple = "hexagon"9 10; CHECK-LABEL: load_store_interleaved:11; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)12; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}13; Function Attrs: mustprogress nounwind14define linkonce_odr dso_local void @load_store_interleaved(ptr %p, float %a, float %b) local_unnamed_addr {15entry:16 %0 = load float, ptr %p, align 817 %add0 = fadd float %0, %a18 store float %add0, ptr %p, align 819 %q = getelementptr i8, ptr %p, i32 420 %1 = load float, ptr %q, align 421 %add1 = fadd float %1, %b22 store float %add1, ptr %q, align 423 ret void24}25 26; Store can be widened here, but this order of instructions is not currently handled27; CHECK-LABEL: loads_between_stores:28; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)29; CHECK-NOT: memd(r{{[0-9]+}}+#4) = r{{[0-9]+}}:{{[0-9]+}}30; Function Attrs: mustprogress nounwind31define linkonce_odr dso_local void @loads_between_stores(ptr %p, float %a, float %b) local_unnamed_addr {32entry:33 %add0 = fadd float %b, %a34 %q = getelementptr i8, ptr %p, i32 435 %r = getelementptr i8, ptr %p, i32 836 store float %add0, ptr %r, align 437 %0 = load float, ptr %p, align 838 %1 = load float, ptr %q, align 439 %add1 = fadd float %1, %040 store float %add1, ptr %q, align 841 ret void42}43 44; CHECK-LABEL: loads_before_stores:45; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)46; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}47; Function Attrs: mustprogress nounwind48define linkonce_odr dso_local void @loads_before_stores(ptr %p, float %a, float %b) local_unnamed_addr {49entry:50 %0 = load float, ptr %p, align 851 %q = getelementptr i8, ptr %p, i32 452 %1 = load float, ptr %q, align 453 %add0 = fadd float %0, %a54 store float %add0, ptr %p, align 855 %add1 = fadd float %1, %b56 store float %add1, ptr %q, align 457 ret void58}59 60; Store can be widened here, but this order of instructions is not currently handled61; CHECK-LABEL: store_load_interleaved:62; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)63; CHECK-NOT: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}64; Function Attrs: mustprogress nounwind65define linkonce_odr dso_local void @store_load_interleaved(ptr %p, float %a, float %b, float %f) local_unnamed_addr {66entry:67 %q = getelementptr i8, ptr %p, i32 468 %r = getelementptr i8, ptr %p, i32 869 store float %f, ptr %r, align 470 %0 = load float, ptr %p, align 871 %add0 = fadd float %0, %a72 store float %add0, ptr %p, align 873 %1 = load float, ptr %q, align 474 %add1 = fadd float %1, %b75 %add2 = fadd float %add1, %add076 store float %add2, ptr %q, align 877 ret void78}79 80; CHECK-LABEL: stores_between_loads:81; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)82; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}83; Function Attrs: mustprogress nounwind84define linkonce_odr dso_local void @stores_between_loads(ptr %p, float %a, float %b, float %f) local_unnamed_addr {85entry:86 %0 = load float, ptr %p, align 887 %add0 = fadd float %f, %088 store float %add0, ptr %p, align 889 %q = getelementptr i8, ptr %p, i32 490 %add1 = fadd float %f, %b91 store float %add1, ptr %q, align 892 %r = getelementptr i8, ptr %p, i32 893 %1 = load float, ptr %r, align 494 %add2 = fadd float %add1, %195 store float %add2, ptr %r, align 496 ret void97}98