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1; RUN: llc < %s | FileCheck %s2 3; Test that basic 32-bit integer comparison operations assemble as expected.4 5target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"6target triple = "lanai"7 8; CHECK-LABEL: eq_i32:9; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r010; CHECK-NEXT: seq11define i32 @eq_i32(i32 %x, i32 %y) {12 %a = icmp eq i32 %x, %y13 %b = zext i1 %a to i3214 ret i32 %b15}16 17; CHECK-LABEL: ne_i32:18; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r019; CHECK-NEXT: sne20define i32 @ne_i32(i32 %x, i32 %y) {21 %a = icmp ne i32 %x, %y22 %b = zext i1 %a to i3223 ret i32 %b24}25 26; CHECK-LABEL: slt_i32:27; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r028; CHECK-NEXT: slt29define i32 @slt_i32(i32 %x, i32 %y) {30 %a = icmp slt i32 %x, %y31 %b = zext i1 %a to i3232 ret i32 %b33}34 35; CHECK-LABEL: sle_i32:36; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r037; CHECK-NEXT: sle38define i32 @sle_i32(i32 %x, i32 %y) {39 %a = icmp sle i32 %x, %y40 %b = zext i1 %a to i3241 ret i32 %b42}43 44; CHECK-LABEL: ult_i32:45; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r046; CHECK-NEXT: sult47define i32 @ult_i32(i32 %x, i32 %y) {48 %a = icmp ult i32 %x, %y49 %b = zext i1 %a to i3250 ret i32 %b51}52 53; CHECK-LABEL: ule_i32:54; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r055; CHECK-NEXT: sule56define i32 @ule_i32(i32 %x, i32 %y) {57 %a = icmp ule i32 %x, %y58 %b = zext i1 %a to i3259 ret i32 %b60}61 62; CHECK-LABEL: sgt_i32:63; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r064; CHECK-NEXT: sgt65define i32 @sgt_i32(i32 %x, i32 %y) {66 %a = icmp sgt i32 %x, %y67 %b = zext i1 %a to i3268 ret i32 %b69}70 71; CHECK-LABEL: sge_i32:72; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r073; CHECK-NEXT: sge74define i32 @sge_i32(i32 %x, i32 %y) {75 %a = icmp sge i32 %x, %y76 %b = zext i1 %a to i3277 ret i32 %b78}79 80; CHECK-LABEL: ugt_i32:81; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r082; CHECK-NEXT: sugt83define i32 @ugt_i32(i32 %x, i32 %y) {84 %a = icmp ugt i32 %x, %y85 %b = zext i1 %a to i3286 ret i32 %b87}88 89; CHECK-LABEL: uge_i32:90; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r091; CHECK-NEXT: suge92define i32 @uge_i32(i32 %x, i32 %y) {93 %a = icmp uge i32 %x, %y94 %b = zext i1 %a to i3295 ret i32 %b96}97