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1; RUN: llc < %s | FileCheck %s2 3; Test that basic 64-bit integer comparison operations assemble as expected.4 5target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"6target triple = "lanai"7 8; CHECK-LABEL: eq_i64:9; CHECK: xor10; CHECK: xor11; CHECK: or.f12; CHECK-NEXT: seq13define i32 @eq_i64(i64 inreg %x, i64 inreg %y) {14 %a = icmp eq i64 %x, %y15 %b = zext i1 %a to i3216 ret i32 %b17}18 19; CHECK-LABEL: ne_i64:20; CHECK: xor21; CHECK: xor22; CHECK: or.f23; CHECK-NEXT: sne24define i32 @ne_i64(i64 inreg %x, i64 inreg %y) {25 %a = icmp ne i64 %x, %y26 %b = zext i1 %a to i3227 ret i32 %b28}29 30; CHECK-LABEL: slt_i64:31; CHECK: sub.f %r6, %r18, %r032; CHECK-NEXT: slt %r333; CHECK-NEXT: sub.f %r7, %r19, %r034; CHECK-NEXT: sult %r935; CHECK-NEXT: sub.f %r6, %r18, %r036; CHECK-NEXT: sel.eq %r9, %r3, %rv37define i32 @slt_i64(i64 inreg %x, i64 inreg %y) {38 %a = icmp slt i64 %x, %y39 %b = zext i1 %a to i3240 ret i32 %b41}42 43; CHECK-LABEL: sle_i64:44; CHECK: sub.f %r6, %r18, %r045; CHECK-NEXT: sle %r346; CHECK-NEXT: sub.f %r7, %r19, %r047; CHECK-NEXT: sule %r948; CHECK-NEXT: sub.f %r6, %r18, %r049; CHECK-NEXT: sel.eq %r9, %r3, %rv50define i32 @sle_i64(i64 inreg %x, i64 inreg %y) {51 %a = icmp sle i64 %x, %y52 %b = zext i1 %a to i3253 ret i32 %b54}55 56; CHECK-LABEL: ult_i64:57; CHECK: sub.f %r6, %r18, %r058; CHECK-NEXT: sult %r359; CHECK-NEXT: sub.f %r7, %r19, %r060; CHECK-NEXT: sult %r961; CHECK-NEXT: sub.f %r6, %r18, %r062; CHECK-NEXT: sel.eq %r9, %r3, %rv63define i32 @ult_i64(i64 inreg %x, i64 inreg %y) {64 %a = icmp ult i64 %x, %y65 %b = zext i1 %a to i3266 ret i32 %b67}68 69; CHECK-LABEL: ule_i64:70; CHECK: sub.f %r6, %r18, %r071; CHECK-NEXT: sule %r372; CHECK-NEXT: sub.f %r7, %r19, %r073; CHECK-NEXT: sule %r974; CHECK-NEXT: sub.f %r6, %r18, %r075; CHECK-NEXT: sel.eq %r9, %r3, %rv76define i32 @ule_i64(i64 inreg %x, i64 inreg %y) {77 %a = icmp ule i64 %x, %y78 %b = zext i1 %a to i3279 ret i32 %b80}81 82; CHECK-LABEL: sgt_i64:83; CHECK: sub.f %r6, %r18, %r084; CHECK-NEXT: sgt %r385; CHECK-NEXT: sub.f %r7, %r19, %r086; CHECK-NEXT: sugt %r987; CHECK-NEXT: sub.f %r6, %r18, %r088; CHECK-NEXT: sel.eq %r9, %r3, %rv89define i32 @sgt_i64(i64 inreg %x, i64 inreg %y) {90 %a = icmp sgt i64 %x, %y91 %b = zext i1 %a to i3292 ret i32 %b93}94 95; CHECK-LABEL: sge_i64:96; CHECK: sub.f %r6, %r18, %r097; CHECK-NEXT: sge %r398; CHECK-NEXT: sub.f %r7, %r19, %r099; CHECK-NEXT: suge %r9100; CHECK-NEXT: sub.f %r6, %r18, %r0101; CHECK-NEXT: sel.eq %r9, %r3, %rv102define i32 @sge_i64(i64 inreg %x, i64 inreg %y) {103 %a = icmp sge i64 %x, %y104 %b = zext i1 %a to i32105 ret i32 %b106}107 108; CHECK-LABEL: ugt_i64:109; CHECK: sub.f %r6, %r18, %r0110; CHECK-NEXT: sugt %r3111; CHECK-NEXT: sub.f %r7, %r19, %r0112; CHECK-NEXT: sugt %r9113; CHECK-NEXT: sub.f %r6, %r18, %r0114; CHECK-NEXT: sel.eq %r9, %r3, %rv115define i32 @ugt_i64(i64 inreg %x, i64 inreg %y) {116 %a = icmp ugt i64 %x, %y117 %b = zext i1 %a to i32118 ret i32 %b119}120 121; CHECK-LABEL: uge_i64:122; CHECK: sub.f %r6, %r18, %r0123; CHECK-NEXT: suge %r3124; CHECK-NEXT: sub.f %r7, %r19, %r0125; CHECK-NEXT: suge %r9126; CHECK-NEXT: sub.f %r6, %r18, %r0127; CHECK-NEXT: sel.eq %r9, %r3, %rv128define i32 @uge_i64(i64 inreg %x, i64 inreg %y) {129 %a = icmp uge i64 %x, %y130 %b = zext i1 %a to i32131 ret i32 %b132}133