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1# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s2# RUN: llc -passes=peephole-opt %s -o - | FileCheck %s3 4# Test the compare fold peephole.5 6# CHECK-LABEL: name: test0a7# TODO: Enhance combiner to handle this case. This expands into:8# sub $r7, $r6, $r39# sub.f $r7, $r6, $r010# sel.eq $r18, $r3, $rv11# This is different from the pattern currently matched. If the lowered form had12# been sub.f $r3, 0, $r0 then it would have matched.13 14# CHECK-LABEL: name: test1a15# CHECK: [[IN1:%.*]]:gpr = COPY $r716# CHECK: [[IN2:%.*]]:gpr = COPY $r617# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr18 19# CHECK-LABEL: name: test1b20# CHECK: [[IN1:%.*]]:gpr = COPY $r721# CHECK: [[IN2:%.*]]:gpr = COPY $r622# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr23 24# CHECK-LABEL: name: test2a25# CHECK: [[IN1:%.*]]:gpr = COPY $r726# CHECK: [[IN2:%.*]]:gpr = COPY $r627# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr28 29# CHECK-LABEL: name: test2b30# CHECK: [[IN1:%.*]]:gpr = COPY $r731# CHECK: [[IN2:%.*]]:gpr = COPY $r632# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr33 34# CHECK-LABEL: name: test335# CHECK: AND_F_R36# CHECK: AND_F_R37# CHECK: AND_F_R38 39--- |40 target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"41 target triple = "lanai-unknown-unknown"42 43 @a = global i32 -1, align 444 @b = global i32 0, align 445 46 define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {47 entry:48 %sub = sub i32 %b, %a49 %cmp = icmp eq i32 %sub, 050 %cond = select i1 %cmp, i32 %c, i32 %sub51 ret i32 %cond52 }53 54 define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {55 entry:56 %cmp = icmp eq i32 %b, %a57 %cond = select i1 %cmp, i32 %c, i32 %b58 ret i32 %cond59 }60 61 define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {62 entry:63 %sub = sub i32 %b, %a64 %cmp = icmp slt i32 %sub, 065 %cond = select i1 %cmp, i32 %c, i32 %d66 ret i32 %cond67 }68 69 define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {70 entry:71 %sub = sub i32 %b, %a72 %cmp = icmp slt i32 %sub, 073 %cond = select i1 %cmp, i32 %c, i32 %d74 ret i32 %cond75 }76 77 define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {78 entry:79 %sub = sub i32 %b, %a80 %cmp = icmp sgt i32 %sub, -181 %cond = select i1 %cmp, i32 %c, i32 %d82 ret i32 %cond83 }84 85 define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {86 entry:87 %sub = sub i32 %b, %a88 %cmp = icmp sgt i32 %sub, -189 %cond = select i1 %cmp, i32 %c, i32 %d90 ret i32 %cond91 }92 93 define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {94 entry:95 %sub = sub i32 %b, %a96 %cmp = icmp slt i32 %sub, 197 %cond = select i1 %cmp, i32 %c, i32 %d98 ret i32 %cond99 }100 101 define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {102 entry:103 %cmp = icmp ne i32 %a, 0104 %cmp1 = icmp ult i32 %a, %b105 %or.cond = and i1 %cmp, %cmp1106 br i1 %or.cond, label %return, label %if.end107 108 if.end: ; preds = %entry109 %cmp2 = icmp ne i32 %b, 0110 %cmp4 = icmp ult i32 %b, %c111 %or.cond29 = and i1 %cmp2, %cmp4112 br i1 %or.cond29, label %return, label %if.end6113 114 if.end6: ; preds = %if.end115 %cmp7 = icmp ne i32 %c, 0116 %cmp9 = icmp ult i32 %c, %d117 %or.cond30 = and i1 %cmp7, %cmp9118 br i1 %or.cond30, label %return, label %if.end11119 120 if.end11: ; preds = %if.end6121 %cmp12 = icmp ne i32 %d, 0122 %cmp14 = icmp ult i32 %d, %a123 %or.cond31 = and i1 %cmp12, %cmp14124 %b. = select i1 %or.cond31, i32 %b, i32 21125 ret i32 %b.126 127 return: ; preds = %if.end6, %if.end, %entry128 %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]129 ret i32 %retval.0130 }131 132 define void @testBB() {133 entry:134 %0 = load i32, ptr @a, align 4, !tbaa !0135 %1 = load i32, ptr @b, align 4, !tbaa !0136 %sub.i = sub i32 %1, %0137 %tobool = icmp sgt i32 %sub.i, -1138 br i1 %tobool, label %if.end, label %if.then139 140 if.then: ; preds = %entry141 %call1 = tail call i32 @g()142 br label %while.body143 144 while.body: ; preds = %while.body, %if.then145 br label %while.body146 147 if.end: ; preds = %entry148 %cmp.i = icmp slt i32 %sub.i, 1149 br i1 %cmp.i, label %if.then4, label %if.end7150 151 if.then4: ; preds = %if.end152 %call5 = tail call i32 @g()153 br label %while.body6154 155 while.body6: ; preds = %while.body6, %if.then4156 br label %while.body6157 158 if.end7: ; preds = %if.end159 ret void160 }161 162 declare i32 @g(...)163 164 ; Function Attrs: nounwind165 declare void @llvm.stackprotector(ptr, ptr) #0166 167 attributes #0 = { nounwind }168 169 !0 = !{!1, !1, i64 0}170 !1 = !{!"int", !2, i64 0}171 !2 = !{!"omnipotent char", !3, i64 0}172 !3 = !{!"Simple C/C++ TBAA"}173 174...175---176name: test0a177alignment: 4178exposesReturnsTwice: false179tracksRegLiveness: true180registers:181 - { id: 0, class: gpr }182 - { id: 1, class: gpr }183 - { id: 2, class: gpr }184 - { id: 3, class: gpr }185 - { id: 4, class: gpr }186 - { id: 5, class: gpr }187liveins:188 - { reg: '$r6', virtual-reg: '%0' }189 - { reg: '$r7', virtual-reg: '%1' }190 - { reg: '$r18', virtual-reg: '%2' }191frameInfo:192 isFrameAddressTaken: false193 isReturnAddressTaken: false194 hasStackMap: false195 hasPatchPoint: false196 stackSize: 0197 offsetAdjustment: 0198 maxAlignment: 0199 adjustsStack: false200 hasCalls: false201 maxCallFrameSize: 0202 hasOpaqueSPAdjustment: false203 hasVAStart: false204 hasMustTailInVarArgFunc: false205body: |206 bb.0.entry:207 liveins: $r6, $r7, $r18208 209 %2 = COPY $r18210 %1 = COPY $r7211 %0 = COPY $r6212 %4 = SUB_R %1, %0, 0213 SFSUB_F_RI_LO %4, 0, implicit-def $sr214 %5 = SELECT %2, %4, 7, implicit $sr215 $rv = COPY %5216 RET implicit $rca, implicit $rv217 218...219---220name: test0b221alignment: 4222exposesReturnsTwice: false223tracksRegLiveness: true224registers:225 - { id: 0, class: gpr }226 - { id: 1, class: gpr }227 - { id: 2, class: gpr }228 - { id: 3, class: gpr }229 - { id: 4, class: gpr }230liveins:231 - { reg: '$r6', virtual-reg: '%0' }232 - { reg: '$r7', virtual-reg: '%1' }233 - { reg: '$r18', virtual-reg: '%2' }234frameInfo:235 isFrameAddressTaken: false236 isReturnAddressTaken: false237 hasStackMap: false238 hasPatchPoint: false239 stackSize: 0240 offsetAdjustment: 0241 maxAlignment: 0242 adjustsStack: false243 hasCalls: false244 maxCallFrameSize: 0245 hasOpaqueSPAdjustment: false246 hasVAStart: false247 hasMustTailInVarArgFunc: false248body: |249 bb.0.entry:250 liveins: $r6, $r7, $r18251 252 %2 = COPY $r18253 %1 = COPY $r7254 %0 = COPY $r6255 SFSUB_F_RR %1, %0, implicit-def $sr256 %4 = SELECT %2, %1, 7, implicit $sr257 $rv = COPY %4258 RET implicit $rca, implicit $rv259 260...261---262name: test1a263alignment: 4264exposesReturnsTwice: false265tracksRegLiveness: true266registers:267 - { id: 0, class: gpr }268 - { id: 1, class: gpr }269 - { id: 2, class: gpr }270 - { id: 3, class: gpr }271 - { id: 4, class: gpr }272 - { id: 5, class: gpr }273liveins:274 - { reg: '$r6', virtual-reg: '%0' }275 - { reg: '$r7', virtual-reg: '%1' }276 - { reg: '$r18', virtual-reg: '%2' }277 - { reg: '$r19', virtual-reg: '%3' }278frameInfo:279 isFrameAddressTaken: false280 isReturnAddressTaken: false281 hasStackMap: false282 hasPatchPoint: false283 stackSize: 0284 offsetAdjustment: 0285 maxAlignment: 0286 adjustsStack: false287 hasCalls: false288 maxCallFrameSize: 0289 hasOpaqueSPAdjustment: false290 hasVAStart: false291 hasMustTailInVarArgFunc: false292body: |293 bb.0.entry:294 liveins: $r6, $r7, $r18, $r19295 296 %3 = COPY $r19297 %2 = COPY $r18298 %1 = COPY $r7299 %0 = COPY $r6300 %4 = SUB_R %1, %0, 0301 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr302 %5 = SELECT %2, %3, 11, implicit $sr303 $rv = COPY %5304 RET implicit $rca, implicit $rv305 306...307---308name: test1b309alignment: 4310exposesReturnsTwice: false311tracksRegLiveness: true312registers:313 - { id: 0, class: gpr }314 - { id: 1, class: gpr }315 - { id: 2, class: gpr }316 - { id: 3, class: gpr }317 - { id: 4, class: gpr }318 - { id: 5, class: gpr }319liveins:320 - { reg: '$r6', virtual-reg: '%0' }321 - { reg: '$r7', virtual-reg: '%1' }322 - { reg: '$r18', virtual-reg: '%2' }323 - { reg: '$r19', virtual-reg: '%3' }324frameInfo:325 isFrameAddressTaken: false326 isReturnAddressTaken: false327 hasStackMap: false328 hasPatchPoint: false329 stackSize: 0330 offsetAdjustment: 0331 maxAlignment: 0332 adjustsStack: false333 hasCalls: false334 maxCallFrameSize: 0335 hasOpaqueSPAdjustment: false336 hasVAStart: false337 hasMustTailInVarArgFunc: false338body: |339 bb.0.entry:340 liveins: $r6, $r7, $r18, $r19341 342 %3 = COPY $r19343 %2 = COPY $r18344 %1 = COPY $r7345 %0 = COPY $r6346 %4 = SUB_R %1, %0, 0347 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr348 %5 = SELECT %2, %3, 11, implicit $sr349 $rv = COPY %5350 RET implicit $rca, implicit $rv351 352...353---354name: test2a355alignment: 4356exposesReturnsTwice: false357tracksRegLiveness: true358registers:359 - { id: 0, class: gpr }360 - { id: 1, class: gpr }361 - { id: 2, class: gpr }362 - { id: 3, class: gpr }363 - { id: 4, class: gpr }364 - { id: 5, class: gpr }365liveins:366 - { reg: '$r6', virtual-reg: '%0' }367 - { reg: '$r7', virtual-reg: '%1' }368 - { reg: '$r18', virtual-reg: '%2' }369 - { reg: '$r19', virtual-reg: '%3' }370frameInfo:371 isFrameAddressTaken: false372 isReturnAddressTaken: false373 hasStackMap: false374 hasPatchPoint: false375 stackSize: 0376 offsetAdjustment: 0377 maxAlignment: 0378 adjustsStack: false379 hasCalls: false380 maxCallFrameSize: 0381 hasOpaqueSPAdjustment: false382 hasVAStart: false383 hasMustTailInVarArgFunc: false384body: |385 bb.0.entry:386 liveins: $r6, $r7, $r18, $r19387 388 %3 = COPY $r19389 %2 = COPY $r18390 %1 = COPY $r7391 %0 = COPY $r6392 %4 = SUB_R %1, %0, 0393 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr394 %5 = SELECT %2, %3, 10, implicit $sr395 $rv = COPY %5396 RET implicit $rca, implicit $rv397 398...399---400name: test2b401alignment: 4402exposesReturnsTwice: false403tracksRegLiveness: true404registers:405 - { id: 0, class: gpr }406 - { id: 1, class: gpr }407 - { id: 2, class: gpr }408 - { id: 3, class: gpr }409 - { id: 4, class: gpr }410 - { id: 5, class: gpr }411liveins:412 - { reg: '$r6', virtual-reg: '%0' }413 - { reg: '$r7', virtual-reg: '%1' }414 - { reg: '$r18', virtual-reg: '%2' }415 - { reg: '$r19', virtual-reg: '%3' }416frameInfo:417 isFrameAddressTaken: false418 isReturnAddressTaken: false419 hasStackMap: false420 hasPatchPoint: false421 stackSize: 0422 offsetAdjustment: 0423 maxAlignment: 0424 adjustsStack: false425 hasCalls: false426 maxCallFrameSize: 0427 hasOpaqueSPAdjustment: false428 hasVAStart: false429 hasMustTailInVarArgFunc: false430body: |431 bb.0.entry:432 liveins: $r6, $r7, $r18, $r19433 434 %3 = COPY $r19435 %2 = COPY $r18436 %1 = COPY $r7437 %0 = COPY $r6438 %4 = SUB_R %1, %0, 0439 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr440 %5 = SELECT %2, %3, 10, implicit $sr441 $rv = COPY %5442 RET implicit $rca, implicit $rv443 444...445---446name: test3447alignment: 4448exposesReturnsTwice: false449tracksRegLiveness: true450registers:451 - { id: 0, class: gpr }452 - { id: 1, class: gpr }453 - { id: 2, class: gpr }454 - { id: 3, class: gpr }455 - { id: 4, class: gpr }456 - { id: 5, class: gpr }457liveins:458 - { reg: '$r6', virtual-reg: '%0' }459 - { reg: '$r7', virtual-reg: '%1' }460 - { reg: '$r18', virtual-reg: '%2' }461 - { reg: '$r19', virtual-reg: '%3' }462frameInfo:463 isFrameAddressTaken: false464 isReturnAddressTaken: false465 hasStackMap: false466 hasPatchPoint: false467 stackSize: 0468 offsetAdjustment: 0469 maxAlignment: 0470 adjustsStack: false471 hasCalls: false472 maxCallFrameSize: 0473 hasOpaqueSPAdjustment: false474 hasVAStart: false475 hasMustTailInVarArgFunc: false476body: |477 bb.0.entry:478 liveins: $r6, $r7, $r18, $r19479 480 %3 = COPY $r19481 %2 = COPY $r18482 %1 = COPY $r7483 %0 = COPY $r6484 %4 = SUB_R %1, %0, 0485 SFSUB_F_RI_LO killed %4, 1, implicit-def $sr486 %5 = SELECT %2, %3, 13, implicit $sr487 $rv = COPY %5488 RET implicit $rca, implicit $rv489 490...491---492name: test4493alignment: 4494exposesReturnsTwice: false495tracksRegLiveness: true496registers:497 - { id: 0, class: gpr }498 - { id: 1, class: gpr }499 - { id: 2, class: gpr }500 - { id: 3, class: gpr }501 - { id: 4, class: gpr }502 - { id: 5, class: gpr }503 - { id: 6, class: gpr }504 - { id: 7, class: gpr }505 - { id: 8, class: gpr }506 - { id: 9, class: gpr }507 - { id: 10, class: gpr }508 - { id: 11, class: gpr }509 - { id: 12, class: gpr }510 - { id: 13, class: gpr }511 - { id: 14, class: gpr }512 - { id: 15, class: gpr }513 - { id: 16, class: gpr }514 - { id: 17, class: gpr }515 - { id: 18, class: gpr }516 - { id: 19, class: gpr }517 - { id: 20, class: gpr }518 - { id: 21, class: gpr }519 - { id: 22, class: gpr }520liveins:521 - { reg: '$r6', virtual-reg: '%1' }522 - { reg: '$r7', virtual-reg: '%2' }523 - { reg: '$r18', virtual-reg: '%3' }524 - { reg: '$r19', virtual-reg: '%4' }525frameInfo:526 isFrameAddressTaken: false527 isReturnAddressTaken: false528 hasStackMap: false529 hasPatchPoint: false530 stackSize: 0531 offsetAdjustment: 0532 maxAlignment: 0533 adjustsStack: false534 hasCalls: false535 maxCallFrameSize: 0536 hasOpaqueSPAdjustment: false537 hasVAStart: false538 hasMustTailInVarArgFunc: false539body: |540 bb.0.entry:541 successors: %bb.4.return, %bb.1.if.end542 liveins: $r6, $r7, $r18, $r19543 544 %4 = COPY $r19545 %3 = COPY $r18546 %2 = COPY $r7547 %1 = COPY $r6548 SFSUB_F_RI_LO %1, 0, implicit-def $sr549 %5 = SCC 6, implicit $sr550 SFSUB_F_RR %1, %2, implicit-def $sr551 %6 = SCC 4, implicit $sr552 %7 = AND_R killed %5, killed %6, 0553 %8 = SLI 1554 %9 = AND_R killed %7, %8, 0555 SFSUB_F_RI_LO killed %9, 0, implicit-def $sr556 BRCC %bb.4.return, 6, implicit $sr557 BT %bb.1.if.end558 559 bb.1.if.end:560 successors: %bb.4.return, %bb.2.if.end6561 562 SFSUB_F_RI_LO %2, 0, implicit-def $sr563 %10 = SCC 6, implicit $sr564 SFSUB_F_RR %2, %3, implicit-def $sr565 %11 = SCC 4, implicit $sr566 %12 = AND_R killed %10, killed %11, 0567 %14 = AND_R killed %12, %8, 0568 SFSUB_F_RI_LO killed %14, 0, implicit-def $sr569 BRCC %bb.4.return, 6, implicit $sr570 BT %bb.2.if.end6571 572 bb.2.if.end6:573 successors: %bb.4.return, %bb.3.if.end11574 575 SFSUB_F_RI_LO %3, 0, implicit-def $sr576 %15 = SCC 6, implicit $sr577 SFSUB_F_RR %3, %4, implicit-def $sr578 %16 = SCC 4, implicit $sr579 %17 = AND_R killed %15, killed %16, 0580 %18 = SLI 1581 %19 = AND_R killed %17, killed %18, 0582 SFSUB_F_RI_LO killed %19, 0, implicit-def $sr583 BRCC %bb.4.return, 6, implicit $sr584 BT %bb.3.if.end11585 586 bb.3.if.end11:587 %20 = SLI 21588 SFSUB_F_RR %4, %1, implicit-def $sr589 %21 = SELECT %2, %20, 4, implicit $sr590 SFSUB_F_RI_LO %4, 0, implicit-def $sr591 %22 = SELECT killed %21, %20, 6, implicit $sr592 $rv = COPY %22593 RET implicit $rca, implicit $rv594 595 bb.4.return:596 %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6597 $rv = COPY %0598 RET implicit $rca, implicit $rv599 600...601---602name: testBB603alignment: 4604exposesReturnsTwice: false605tracksRegLiveness: true606registers:607 - { id: 0, class: gpr }608 - { id: 1, class: gpr }609 - { id: 2, class: gpr }610 - { id: 3, class: gpr }611 - { id: 4, class: gpr }612 - { id: 5, class: gpr }613 - { id: 6, class: gpr }614 - { id: 7, class: gpr }615 - { id: 8, class: gpr }616frameInfo:617 isFrameAddressTaken: false618 isReturnAddressTaken: false619 hasStackMap: false620 hasPatchPoint: false621 stackSize: 0622 offsetAdjustment: 0623 maxAlignment: 0624 adjustsStack: false625 hasCalls: true626 maxCallFrameSize: 0627 hasOpaqueSPAdjustment: false628 hasVAStart: false629 hasMustTailInVarArgFunc: false630body: |631 bb.0.entry:632 successors: %bb.3.if.end, %bb.1.if.then633 634 %1 = MOVHI target-flags(lanai-hi) @a635 %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a636 %3 = LDW_RI killed %2, 0, 0 :: (load (s32) from @a, !tbaa !0)637 %4 = MOVHI target-flags(lanai-hi) @b638 %5 = OR_I_LO killed %4, target-flags(lanai-lo) @b639 %6 = LDW_RI killed %5, 0, 0 :: (load (s32) from @b, !tbaa !0)640 %0 = SUB_R killed %6, killed %3, 0641 SFSUB_F_RI_LO %0, 0, implicit-def $sr642 BRCC %bb.3.if.end, 10, implicit $sr643 BT %bb.1.if.then644 645 bb.1.if.then:646 successors: %bb.2.while.body647 648 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp649 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv650 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp651 652 bb.2.while.body:653 successors: %bb.2.while.body654 655 BT %bb.2.while.body656 657 bb.3.if.end:658 successors: %bb.4.if.then4, %bb.6.if.end7659 liveins: $sr660 661 BRCC %bb.6.if.end7, 14, implicit $sr662 BT %bb.4.if.then4663 664 bb.4.if.then4:665 successors: %bb.5.while.body6666 667 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp668 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv669 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp670 671 bb.5.while.body6:672 successors: %bb.5.while.body6673 674 BT %bb.5.while.body6675 676 bb.6.if.end7:677 RET implicit $rca678 679...680