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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=lanai | FileCheck %s3 4define i32 @f(i32 inreg %a, i32 inreg %b) nounwind ssp {5; CHECK-LABEL: f:6; CHECK: ! %bb.0:7; CHECK-NEXT: st %fp, [--%sp]8; CHECK-NEXT: add %sp, 0x8, %fp9; CHECK-NEXT: sub %sp, 0x8, %sp10; CHECK-NEXT: sub.f %r6, %r7, %r311; CHECK-NEXT: sel.gt %r3, %r0, %rv12; CHECK-NEXT: ld -4[%fp], %pc ! return13; CHECK-NEXT: add %fp, 0x0, %sp14; CHECK-NEXT: ld -8[%fp], %fp15 %cmp = icmp sgt i32 %a, %b16 %sub = sub nsw i32 %a, %b17 %sub. = select i1 %cmp, i32 %sub, i32 018 ret i32 %sub.19}20 21define i32 @g(i32 inreg %a, i32 inreg %b) nounwind ssp {22; CHECK-LABEL: g:23; CHECK: ! %bb.0:24; CHECK-NEXT: st %fp, [--%sp]25; CHECK-NEXT: add %sp, 0x8, %fp26; CHECK-NEXT: sub %sp, 0x8, %sp27; CHECK-NEXT: sub.f %r7, %r6, %r328; CHECK-NEXT: sel.gt %r3, %r0, %rv29; CHECK-NEXT: ld -4[%fp], %pc ! return30; CHECK-NEXT: add %fp, 0x0, %sp31; CHECK-NEXT: ld -8[%fp], %fp32 %cmp = icmp slt i32 %a, %b33 %sub = sub nsw i32 %b, %a34 %sub. = select i1 %cmp, i32 %sub, i32 035 ret i32 %sub.36}37 38define i32 @h(i32 inreg %a, i32 inreg %b) nounwind ssp {39; CHECK-LABEL: h:40; CHECK: ! %bb.0:41; CHECK-NEXT: st %fp, [--%sp]42; CHECK-NEXT: add %sp, 0x8, %fp43; CHECK-NEXT: sub %sp, 0x8, %sp44; CHECK-NEXT: sub.f %r6, 0x3, %r345; CHECK-NEXT: sel.gt %r3, %r7, %rv46; CHECK-NEXT: ld -4[%fp], %pc ! return47; CHECK-NEXT: add %fp, 0x0, %sp48; CHECK-NEXT: ld -8[%fp], %fp49 %cmp = icmp sgt i32 %a, 350 %sub = sub nsw i32 %a, 351 %sub. = select i1 %cmp, i32 %sub, i32 %b52 ret i32 %sub.53}54 55define i32 @i(i32 inreg %a, i32 inreg %b) nounwind readnone ssp {56; CHECK-LABEL: i:57; CHECK: ! %bb.0:58; CHECK-NEXT: st %fp, [--%sp]59; CHECK-NEXT: add %sp, 0x8, %fp60; CHECK-NEXT: sub %sp, 0x8, %sp61; CHECK-NEXT: sub.f %r7, %r6, %r362; CHECK-NEXT: sel.ugt %r3, %r0, %rv63; CHECK-NEXT: ld -4[%fp], %pc ! return64; CHECK-NEXT: add %fp, 0x0, %sp65; CHECK-NEXT: ld -8[%fp], %fp66 %cmp = icmp ult i32 %a, %b67 %sub = sub i32 %b, %a68 %sub. = select i1 %cmp, i32 %sub, i32 069 ret i32 %sub.70}71 72; If SR is live-out, we can't remove cmp if there exists a swapped sub.73define i32 @j(i32 inreg %a, i32 inreg %b) nounwind {74; CHECK-LABEL: j:75; CHECK: ! %bb.0: ! %entry76; CHECK-NEXT: st %fp, [--%sp]77; CHECK-NEXT: add %sp, 0x8, %fp78; CHECK-NEXT: sub %sp, 0x8, %sp79; CHECK-NEXT: sub.f %r6, %r7, %r080; CHECK-NEXT: bne .LBB4_281; CHECK-NEXT: sub %r6, %r7, %rv82; CHECK-NEXT: .LBB4_1: ! %if.then83; CHECK-NEXT: sel.lt %rv, %r6, %rv84; CHECK-NEXT: .LBB4_2: ! %if.else85; CHECK-NEXT: ld -4[%fp], %pc ! return86; CHECK-NEXT: add %fp, 0x0, %sp87; CHECK-NEXT: ld -8[%fp], %fp88entry:89 %cmp = icmp eq i32 %b, %a90 %sub = sub nsw i32 %a, %b91 br i1 %cmp, label %if.then, label %if.else92 93if.then:94 %cmp2 = icmp sgt i32 %b, %a95 %sel = select i1 %cmp2, i32 %sub, i32 %a96 ret i32 %sel97 98if.else:99 ret i32 %sub100}101 102declare void @abort()103declare void @exit(i32)104@t = common global i32 0105 106; If the comparison uses the C bit (signed overflow/underflow), we can't107; omit the comparison.108define i32 @cmp_ult0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {109; CHECK-LABEL: cmp_ult0:110; CHECK: ! %bb.0: ! %entry111; CHECK-NEXT: st %fp, [--%sp]112; CHECK-NEXT: add %sp, 0x8, %fp113; CHECK-NEXT: mov hi(t), %r3114; CHECK-NEXT: or %r3, lo(t), %r3115; CHECK-NEXT: ld 0[%r3], %r3116; CHECK-NEXT: sub %r3, 0x11, %r3117; CHECK-NEXT: sub.f %r3, 0x0, %r0118; CHECK-NEXT: buge .LBB5_2119; CHECK-NEXT: sub %sp, 0x10, %sp120; CHECK-NEXT: .LBB5_1: ! %if.then121; CHECK-NEXT: add %pc, 0x10, %rca122; CHECK-NEXT: st %rca, [--%sp]123; CHECK-NEXT: bt abort124; CHECK-NEXT: nop125; CHECK-NEXT: .LBB5_2: ! %if.else126; CHECK-NEXT: st %r0, 0[%sp]127; CHECK-NEXT: add %pc, 0x10, %rca128; CHECK-NEXT: st %rca, [--%sp]129; CHECK-NEXT: bt exit130; CHECK-NEXT: nop131entry:132 %load = load i32, ptr @t, align 4133 %sub = sub i32 %load, 17134 %cmp = icmp ult i32 %sub, 0135 br i1 %cmp, label %if.then, label %if.else136 137if.then:138 call void @abort()139 unreachable140 141if.else:142 call void @exit(i32 0)143 unreachable144}145 146; Same for the V bit.147; TODO: add test that exercises V bit individually (VC/VS).148define i32 @cmp_gt0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {149; CHECK-LABEL: cmp_gt0:150; CHECK: ! %bb.0: ! %entry151; CHECK-NEXT: st %fp, [--%sp]152; CHECK-NEXT: add %sp, 0x8, %fp153; CHECK-NEXT: mov hi(t), %r3154; CHECK-NEXT: or %r3, lo(t), %r3155; CHECK-NEXT: ld 0[%r3], %r3156; CHECK-NEXT: sub %r3, 0x11, %r3157; CHECK-NEXT: sub.f %r3, 0x1, %r0158; CHECK-NEXT: blt .LBB6_2159; CHECK-NEXT: sub %sp, 0x10, %sp160; CHECK-NEXT: .LBB6_1: ! %if.then161; CHECK-NEXT: add %pc, 0x10, %rca162; CHECK-NEXT: st %rca, [--%sp]163; CHECK-NEXT: bt abort164; CHECK-NEXT: nop165; CHECK-NEXT: .LBB6_2: ! %if.else166; CHECK-NEXT: st %r0, 0[%sp]167; CHECK-NEXT: add %pc, 0x10, %rca168; CHECK-NEXT: st %rca, [--%sp]169; CHECK-NEXT: bt exit170; CHECK-NEXT: nop171entry:172 %load = load i32, ptr @t, align 4173 %sub = sub i32 %load, 17174 %cmp = icmp sgt i32 %sub, 0175 br i1 %cmp, label %if.then, label %if.else176 177if.then:178 call void @abort()179 unreachable180 181if.else:182 call void @exit(i32 0)183 unreachable184}185