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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch64 --mattr=+f,+d < %s | FileCheck %s --check-prefix=LA643 4; Check the GHC call convention works (la64)5 6@base = external dso_local global i64 ; assigned to register: s07@sp = external dso_local global i64 ; assigned to register: s18@hp = external dso_local global i64 ; assigned to register: s29@r1 = external dso_local global i64 ; assigned to register: s310@r2 = external dso_local global i64 ; assigned to register: s411@r3 = external dso_local global i64 ; assigned to register: s512@r4 = external dso_local global i64 ; assigned to register: s613@r5 = external dso_local global i64 ; assigned to register: s714@splim = external dso_local global i64 ; assigned to register: s815 16@f1 = external dso_local global float ; assigned to register: fs017@f2 = external dso_local global float ; assigned to register: fs118@f3 = external dso_local global float ; assigned to register: fs219@f4 = external dso_local global float ; assigned to register: fs320 21@d1 = external dso_local global double ; assigned to register: fs422@d2 = external dso_local global double ; assigned to register: fs523@d3 = external dso_local global double ; assigned to register: fs624@d4 = external dso_local global double ; assigned to register: fs725 26define ghccc void @foo() nounwind {27; LA64-LABEL: foo:28; LA64: # %bb.0: # %entry29; LA64-NEXT: pcalau12i $a0, %pc_hi20(d4)30; LA64-NEXT: fld.d $fs7, $a0, %pc_lo12(d4)31; LA64-NEXT: pcalau12i $a0, %pc_hi20(d3)32; LA64-NEXT: fld.d $fs6, $a0, %pc_lo12(d3)33; LA64-NEXT: pcalau12i $a0, %pc_hi20(d2)34; LA64-NEXT: fld.d $fs5, $a0, %pc_lo12(d2)35; LA64-NEXT: pcalau12i $a0, %pc_hi20(d1)36; LA64-NEXT: fld.d $fs4, $a0, %pc_lo12(d1)37; LA64-NEXT: pcalau12i $a0, %pc_hi20(f4)38; LA64-NEXT: fld.s $fs3, $a0, %pc_lo12(f4)39; LA64-NEXT: pcalau12i $a0, %pc_hi20(f3)40; LA64-NEXT: fld.s $fs2, $a0, %pc_lo12(f3)41; LA64-NEXT: pcalau12i $a0, %pc_hi20(f2)42; LA64-NEXT: fld.s $fs1, $a0, %pc_lo12(f2)43; LA64-NEXT: pcalau12i $a0, %pc_hi20(f1)44; LA64-NEXT: fld.s $fs0, $a0, %pc_lo12(f1)45; LA64-NEXT: pcalau12i $a0, %pc_hi20(splim)46; LA64-NEXT: ld.d $s8, $a0, %pc_lo12(splim)47; LA64-NEXT: pcalau12i $a0, %pc_hi20(r5)48; LA64-NEXT: ld.d $s7, $a0, %pc_lo12(r5)49; LA64-NEXT: pcalau12i $a0, %pc_hi20(r4)50; LA64-NEXT: ld.d $s6, $a0, %pc_lo12(r4)51; LA64-NEXT: pcalau12i $a0, %pc_hi20(r3)52; LA64-NEXT: ld.d $s5, $a0, %pc_lo12(r3)53; LA64-NEXT: pcalau12i $a0, %pc_hi20(r2)54; LA64-NEXT: ld.d $s4, $a0, %pc_lo12(r2)55; LA64-NEXT: pcalau12i $a0, %pc_hi20(r1)56; LA64-NEXT: ld.d $s3, $a0, %pc_lo12(r1)57; LA64-NEXT: pcalau12i $a0, %pc_hi20(hp)58; LA64-NEXT: ld.d $s2, $a0, %pc_lo12(hp)59; LA64-NEXT: pcalau12i $a0, %pc_hi20(sp)60; LA64-NEXT: ld.d $s1, $a0, %pc_lo12(sp)61; LA64-NEXT: pcalau12i $a0, %pc_hi20(base)62; LA64-NEXT: ld.d $s0, $a0, %pc_lo12(base)63; LA64-NEXT: pcaddu18i $t8, %call36(bar)64; LA64-NEXT: jr $t865 66entry:67 %0 = load double, ptr @d468 %1 = load double, ptr @d369 %2 = load double, ptr @d270 %3 = load double, ptr @d171 %4 = load float, ptr @f472 %5 = load float, ptr @f373 %6 = load float, ptr @f274 %7 = load float, ptr @f175 %8 = load i64, ptr @splim76 %9 = load i64, ptr @r577 %10 = load i64, ptr @r478 %11 = load i64, ptr @r379 %12 = load i64, ptr @r280 %13 = load i64, ptr @r181 %14 = load i64, ptr @hp82 %15 = load i64, ptr @sp83 %16 = load i64, ptr @base84 tail call ghccc void @bar(i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,85 i64 %11, i64 %10, i64 %9, i64 %8, float %7, float %6,86 float %5, float %4, double %3, double %2, double %1, double %0) nounwind87 ret void88}89declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64,90 float, float, float, float,91 double, double, double, double)92