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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s3 4define i64 @imm0() {5; CHECK-LABEL: imm0:6; CHECK: # %bb.0:7; CHECK-NEXT: move $a0, $zero8; CHECK-NEXT: ret9 ret i64 010}11 12define i64 @imm7ff0000000000000() {13; CHECK-LABEL: imm7ff0000000000000:14; CHECK: # %bb.0:15; CHECK-NEXT: lu52i.d $a0, $zero, 204716; CHECK-NEXT: ret17 ret i64 921886843722740531218}19 20define i64 @imm0000000000000fff() {21; CHECK-LABEL: imm0000000000000fff:22; CHECK: # %bb.0:23; CHECK-NEXT: ori $a0, $zero, 409524; CHECK-NEXT: ret25 ret i64 409526}27 28define i64 @imm0007ffff00000800() {29; CHECK-LABEL: imm0007ffff00000800:30; CHECK: # %bb.0:31; CHECK-NEXT: ori $a0, $zero, 204832; CHECK-NEXT: lu32i.d $a0, 52428733; CHECK-NEXT: ret34 ret i64 225179551872000035}36 37define i64 @immfff0000000000fff() {38; CHECK-LABEL: immfff0000000000fff:39; CHECK: # %bb.0:40; CHECK-NEXT: ori $a0, $zero, 409541; CHECK-NEXT: lu52i.d $a0, $a0, -142; CHECK-NEXT: ret43 ret i64 -450359962736640144}45 46define i64 @imm0008000000000fff() {47; CHECK-LABEL: imm0008000000000fff:48; CHECK: # %bb.0:49; CHECK-NEXT: ori $a0, $zero, 409550; CHECK-NEXT: bstrins.d $a0, $a0, 51, 5151; CHECK-NEXT: ret52 ret i64 225179981368934353}54 55define i64 @immfffffffffffff800() {56; CHECK-LABEL: immfffffffffffff800:57; CHECK: # %bb.0:58; CHECK-NEXT: addi.w $a0, $zero, -204859; CHECK-NEXT: ret60 ret i64 -204861}62 63define i64 @imm00000000fffff800() {64; CHECK-LABEL: imm00000000fffff800:65; CHECK: # %bb.0:66; CHECK-NEXT: addi.w $a0, $zero, -204867; CHECK-NEXT: lu32i.d $a0, 068; CHECK-NEXT: ret69 ret i64 429496524870}71 72define i64 @imm000ffffffffff800() {73; CHECK-LABEL: imm000ffffffffff800:74; CHECK: # %bb.0:75; CHECK-NEXT: addi.w $a0, $zero, -204876; CHECK-NEXT: lu52i.d $a0, $a0, 077; CHECK-NEXT: ret78 ret i64 450359962736844879}80 81define i64 @imm00080000fffff800() {82; CHECK-LABEL: imm00080000fffff800:83; CHECK: # %bb.0:84; CHECK-NEXT: addi.w $a0, $zero, -204885; CHECK-NEXT: lu32i.d $a0, -52428886; CHECK-NEXT: lu52i.d $a0, $a0, 087; CHECK-NEXT: ret88 ret i64 225180410865049689}90 91define i64 @imm000000007ffff000() {92; CHECK-LABEL: imm000000007ffff000:93; CHECK: # %bb.0:94; CHECK-NEXT: lu12i.w $a0, 52428795; CHECK-NEXT: ret96 ret i64 214747955297}98 99define i64 @imm0000000080000000() {100; CHECK-LABEL: imm0000000080000000:101; CHECK: # %bb.0:102; CHECK-NEXT: lu12i.w $a0, -524288103; CHECK-NEXT: lu32i.d $a0, 0104; CHECK-NEXT: ret105 ret i64 2147483648106}107 108define i64 @imm000ffffffffff000() {109; CHECK-LABEL: imm000ffffffffff000:110; CHECK: # %bb.0:111; CHECK-NEXT: lu12i.w $a0, -1112; CHECK-NEXT: lu52i.d $a0, $a0, 0113; CHECK-NEXT: ret114 ret i64 4503599627366400115}116 117define i64 @imm7ff0000080000000() {118; CHECK-LABEL: imm7ff0000080000000:119; CHECK: # %bb.0:120; CHECK-NEXT: lu12i.w $a0, -524288121; CHECK-NEXT: lu32i.d $a0, 0122; CHECK-NEXT: lu52i.d $a0, $a0, 2047123; CHECK-NEXT: ret124 ret i64 9218868439374888960125}126 127define i64 @immffffffff80000800() {128; CHECK-LABEL: immffffffff80000800:129; CHECK: # %bb.0:130; CHECK-NEXT: lu12i.w $a0, -524288131; CHECK-NEXT: ori $a0, $a0, 2048132; CHECK-NEXT: ret133 ret i64 -2147481600134}135 136define i64 @immffffffff7ffff800() {137; CHECK-LABEL: immffffffff7ffff800:138; CHECK: # %bb.0:139; CHECK-NEXT: lu12i.w $a0, 524287140; CHECK-NEXT: ori $a0, $a0, 2048141; CHECK-NEXT: lu32i.d $a0, -1142; CHECK-NEXT: ret143 ret i64 -2147485696144}145 146define i64 @imm7fffffff800007ff() {147; CHECK-LABEL: imm7fffffff800007ff:148; CHECK: # %bb.0:149; CHECK-NEXT: lu12i.w $a0, -524288150; CHECK-NEXT: ori $a0, $a0, 2047151; CHECK-NEXT: lu52i.d $a0, $a0, 2047152; CHECK-NEXT: ret153 ret i64 9223372034707294207154}155 156define i64 @imm0008000080000800() {157; CHECK-LABEL: imm0008000080000800:158; CHECK: # %bb.0:159; CHECK-NEXT: lu12i.w $a0, -524288160; CHECK-NEXT: ori $a0, $a0, 2048161; CHECK-NEXT: lu32i.d $a0, -524288162; CHECK-NEXT: lu52i.d $a0, $a0, 0163; CHECK-NEXT: ret164 ret i64 2251801961170944165}166 167define i64 @imm14000000a() {168; CHECK-LABEL: imm14000000a:169; CHECK: # %bb.0:170; CHECK-NEXT: ori $a0, $zero, 10171; CHECK-NEXT: bstrins.d $a0, $a0, 32, 29172; CHECK-NEXT: ret173 ret i64 5368709130174}175 176define i64 @imm0fff000000000fff() {177; CHECK-LABEL: imm0fff000000000fff:178; CHECK: # %bb.0:179; CHECK-NEXT: ori $a0, $zero, 4095180; CHECK-NEXT: bstrins.d $a0, $a0, 59, 48181; CHECK-NEXT: ret182 ret i64 1152640029630140415183}184 185define i64 @immffecffffffffffec() {186; CHECK-LABEL: immffecffffffffffec:187; CHECK: # %bb.0:188; CHECK-NEXT: addi.w $a0, $zero, -20189; CHECK-NEXT: bstrins.d $a0, $a0, 52, 48190; CHECK-NEXT: ret191 ret i64 -5348024557502484192}193 194define i64 @imm1c000000700000() {195; CHECK-LABEL: imm1c000000700000:196; CHECK: # %bb.0:197; CHECK-NEXT: lu12i.w $a0, 1792198; CHECK-NEXT: bstrins.d $a0, $a0, 52, 30199; CHECK-NEXT: ret200 ret i64 7881299355238400201}202 203define i64 @immf0f0f0f0f0f0f0f0() {204; CHECK-LABEL: immf0f0f0f0f0f0f0f0:205; CHECK: # %bb.0:206; CHECK-NEXT: lu12i.w $a0, -61681207; CHECK-NEXT: ori $a0, $a0, 240208; CHECK-NEXT: bstrins.d $a0, $a0, 59, 32209; CHECK-NEXT: ret210 ret i64 -1085102592571150096211}212 213define i64 @imm110000014000000a() {214; CHECK-LABEL: imm110000014000000a:215; CHECK: # %bb.0:216; CHECK-NEXT: ori $a0, $zero, 10217; CHECK-NEXT: lu52i.d $a0, $a0, 272218; CHECK-NEXT: bstrins.d $a0, $a0, 32, 29219; CHECK-NEXT: ret220 ret i64 1224979104013484042221}222