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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc --mtriple=loongarch32 --mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK323; RUN: llc --mtriple=loongarch64 --mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK644 5define i1 @isnan_d(double %x) {6; CHECK32-LABEL: isnan_d:7; CHECK32: # %bb.0: # %entry8; CHECK32-NEXT: fclass.d $fa0, $fa09; CHECK32-NEXT: movfr2gr.s $a0, $fa010; CHECK32-NEXT: andi $a0, $a0, 311; CHECK32-NEXT: sltu $a0, $zero, $a012; CHECK32-NEXT: ret13;14; CHECK64-LABEL: isnan_d:15; CHECK64: # %bb.0: # %entry16; CHECK64-NEXT: fclass.d $fa0, $fa017; CHECK64-NEXT: movfr2gr.d $a0, $fa018; CHECK64-NEXT: andi $a0, $a0, 319; CHECK64-NEXT: sltu $a0, $zero, $a020; CHECK64-NEXT: ret21entry:22 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; "nan"23 ret i1 %024}25 26define i1 @isnot_nan_d(double %x) {27; CHECK32-LABEL: isnot_nan_d:28; CHECK32: # %bb.0: # %entry29; CHECK32-NEXT: fclass.d $fa0, $fa030; CHECK32-NEXT: movfr2gr.s $a0, $fa031; CHECK32-NEXT: andi $a0, $a0, 102032; CHECK32-NEXT: sltu $a0, $zero, $a033; CHECK32-NEXT: ret34;35; CHECK64-LABEL: isnot_nan_d:36; CHECK64: # %bb.0: # %entry37; CHECK64-NEXT: fclass.d $fa0, $fa038; CHECK64-NEXT: movfr2gr.d $a0, $fa039; CHECK64-NEXT: andi $a0, $a0, 102040; CHECK64-NEXT: sltu $a0, $zero, $a041; CHECK64-NEXT: ret42entry:43 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"44 ret i1 %045}46 47define i1 @issignaling_d(double %x) {48; CHECK32-LABEL: issignaling_d:49; CHECK32: # %bb.0: # %entry50; CHECK32-NEXT: fclass.d $fa0, $fa051; CHECK32-NEXT: movfr2gr.s $a0, $fa052; CHECK32-NEXT: andi $a0, $a0, 153; CHECK32-NEXT: sltu $a0, $zero, $a054; CHECK32-NEXT: ret55;56; CHECK64-LABEL: issignaling_d:57; CHECK64: # %bb.0: # %entry58; CHECK64-NEXT: fclass.d $fa0, $fa059; CHECK64-NEXT: movfr2gr.d $a0, $fa060; CHECK64-NEXT: andi $a0, $a0, 161; CHECK64-NEXT: sltu $a0, $zero, $a062; CHECK64-NEXT: ret63entry:64 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1) ; "snan"65 ret i1 %066}67 68define i1 @not_issignaling_d(double %x) {69; CHECK32-LABEL: not_issignaling_d:70; CHECK32: # %bb.0: # %entry71; CHECK32-NEXT: fclass.d $fa0, $fa072; CHECK32-NEXT: movfr2gr.s $a0, $fa073; CHECK32-NEXT: andi $a0, $a0, 102274; CHECK32-NEXT: sltu $a0, $zero, $a075; CHECK32-NEXT: ret76;77; CHECK64-LABEL: not_issignaling_d:78; CHECK64: # %bb.0: # %entry79; CHECK64-NEXT: fclass.d $fa0, $fa080; CHECK64-NEXT: movfr2gr.d $a0, $fa081; CHECK64-NEXT: andi $a0, $a0, 102282; CHECK64-NEXT: sltu $a0, $zero, $a083; CHECK64-NEXT: ret84entry:85 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1022) ; ~"snan"86 ret i1 %087}88 89define i1 @isquiet_d(double %x) {90; CHECK32-LABEL: isquiet_d:91; CHECK32: # %bb.0: # %entry92; CHECK32-NEXT: fclass.d $fa0, $fa093; CHECK32-NEXT: movfr2gr.s $a0, $fa094; CHECK32-NEXT: andi $a0, $a0, 295; CHECK32-NEXT: sltu $a0, $zero, $a096; CHECK32-NEXT: ret97;98; CHECK64-LABEL: isquiet_d:99; CHECK64: # %bb.0: # %entry100; CHECK64-NEXT: fclass.d $fa0, $fa0101; CHECK64-NEXT: movfr2gr.d $a0, $fa0102; CHECK64-NEXT: andi $a0, $a0, 2103; CHECK64-NEXT: sltu $a0, $zero, $a0104; CHECK64-NEXT: ret105entry:106 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 2) ; "qnan"107 ret i1 %0108}109 110define i1 @not_isquiet_d(double %x) {111; CHECK32-LABEL: not_isquiet_d:112; CHECK32: # %bb.0: # %entry113; CHECK32-NEXT: fclass.d $fa0, $fa0114; CHECK32-NEXT: movfr2gr.s $a0, $fa0115; CHECK32-NEXT: andi $a0, $a0, 1021116; CHECK32-NEXT: sltu $a0, $zero, $a0117; CHECK32-NEXT: ret118;119; CHECK64-LABEL: not_isquiet_d:120; CHECK64: # %bb.0: # %entry121; CHECK64-NEXT: fclass.d $fa0, $fa0122; CHECK64-NEXT: movfr2gr.d $a0, $fa0123; CHECK64-NEXT: andi $a0, $a0, 1021124; CHECK64-NEXT: sltu $a0, $zero, $a0125; CHECK64-NEXT: ret126entry:127 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1021) ; ~"qnan"128 ret i1 %0129}130 131define i1 @isinf_d(double %x) {132; CHECK32-LABEL: isinf_d:133; CHECK32: # %bb.0: # %entry134; CHECK32-NEXT: fclass.d $fa0, $fa0135; CHECK32-NEXT: movfr2gr.s $a0, $fa0136; CHECK32-NEXT: andi $a0, $a0, 68137; CHECK32-NEXT: sltu $a0, $zero, $a0138; CHECK32-NEXT: ret139;140; CHECK64-LABEL: isinf_d:141; CHECK64: # %bb.0: # %entry142; CHECK64-NEXT: fclass.d $fa0, $fa0143; CHECK64-NEXT: movfr2gr.d $a0, $fa0144; CHECK64-NEXT: andi $a0, $a0, 68145; CHECK64-NEXT: sltu $a0, $zero, $a0146; CHECK64-NEXT: ret147entry:148 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516) ; 0x204 = "inf"149 ret i1 %0150}151 152define i1 @not_isinf_d(double %x) {153; CHECK32-LABEL: not_isinf_d:154; CHECK32: # %bb.0: # %entry155; CHECK32-NEXT: fclass.d $fa0, $fa0156; CHECK32-NEXT: movfr2gr.s $a0, $fa0157; CHECK32-NEXT: andi $a0, $a0, 955158; CHECK32-NEXT: sltu $a0, $zero, $a0159; CHECK32-NEXT: ret160;161; CHECK64-LABEL: not_isinf_d:162; CHECK64: # %bb.0: # %entry163; CHECK64-NEXT: fclass.d $fa0, $fa0164; CHECK64-NEXT: movfr2gr.d $a0, $fa0165; CHECK64-NEXT: andi $a0, $a0, 955166; CHECK64-NEXT: sltu $a0, $zero, $a0167; CHECK64-NEXT: ret168entry:169 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 507) ; ~0x204 = "~inf"170 ret i1 %0171}172 173define i1 @is_plus_inf_d(double %x) {174; CHECK32-LABEL: is_plus_inf_d:175; CHECK32: # %bb.0: # %entry176; CHECK32-NEXT: fclass.d $fa0, $fa0177; CHECK32-NEXT: movfr2gr.s $a0, $fa0178; CHECK32-NEXT: andi $a0, $a0, 64179; CHECK32-NEXT: sltu $a0, $zero, $a0180; CHECK32-NEXT: ret181;182; CHECK64-LABEL: is_plus_inf_d:183; CHECK64: # %bb.0: # %entry184; CHECK64-NEXT: fclass.d $fa0, $fa0185; CHECK64-NEXT: movfr2gr.d $a0, $fa0186; CHECK64-NEXT: andi $a0, $a0, 64187; CHECK64-NEXT: sltu $a0, $zero, $a0188; CHECK64-NEXT: ret189entry:190 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 512) ; 0x200 = "+inf"191 ret i1 %0192}193 194define i1 @is_minus_inf_d(double %x) {195; CHECK32-LABEL: is_minus_inf_d:196; CHECK32: # %bb.0: # %entry197; CHECK32-NEXT: fclass.d $fa0, $fa0198; CHECK32-NEXT: movfr2gr.s $a0, $fa0199; CHECK32-NEXT: andi $a0, $a0, 4200; CHECK32-NEXT: sltu $a0, $zero, $a0201; CHECK32-NEXT: ret202;203; CHECK64-LABEL: is_minus_inf_d:204; CHECK64: # %bb.0: # %entry205; CHECK64-NEXT: fclass.d $fa0, $fa0206; CHECK64-NEXT: movfr2gr.d $a0, $fa0207; CHECK64-NEXT: andi $a0, $a0, 4208; CHECK64-NEXT: sltu $a0, $zero, $a0209; CHECK64-NEXT: ret210entry:211 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 4) ; "-inf"212 ret i1 %0213}214 215define i1 @not_is_minus_inf_d(double %x) {216; CHECK32-LABEL: not_is_minus_inf_d:217; CHECK32: # %bb.0: # %entry218; CHECK32-NEXT: fclass.d $fa0, $fa0219; CHECK32-NEXT: movfr2gr.s $a0, $fa0220; CHECK32-NEXT: andi $a0, $a0, 1019221; CHECK32-NEXT: sltu $a0, $zero, $a0222; CHECK32-NEXT: ret223;224; CHECK64-LABEL: not_is_minus_inf_d:225; CHECK64: # %bb.0: # %entry226; CHECK64-NEXT: fclass.d $fa0, $fa0227; CHECK64-NEXT: movfr2gr.d $a0, $fa0228; CHECK64-NEXT: andi $a0, $a0, 1019229; CHECK64-NEXT: sltu $a0, $zero, $a0230; CHECK64-NEXT: ret231entry:232 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1019) ; ~"-inf"233 ret i1 %0234}235 236define i1 @isfinite_d(double %x) {237; CHECK32-LABEL: isfinite_d:238; CHECK32: # %bb.0: # %entry239; CHECK32-NEXT: fclass.d $fa0, $fa0240; CHECK32-NEXT: movfr2gr.s $a0, $fa0241; CHECK32-NEXT: andi $a0, $a0, 952242; CHECK32-NEXT: sltu $a0, $zero, $a0243; CHECK32-NEXT: ret244;245; CHECK64-LABEL: isfinite_d:246; CHECK64: # %bb.0: # %entry247; CHECK64-NEXT: fclass.d $fa0, $fa0248; CHECK64-NEXT: movfr2gr.d $a0, $fa0249; CHECK64-NEXT: andi $a0, $a0, 952250; CHECK64-NEXT: sltu $a0, $zero, $a0251; CHECK64-NEXT: ret252entry:253 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite"254 ret i1 %0255}256 257define i1 @not_isfinite_d(double %x) {258; CHECK32-LABEL: not_isfinite_d:259; CHECK32: # %bb.0: # %entry260; CHECK32-NEXT: fclass.d $fa0, $fa0261; CHECK32-NEXT: movfr2gr.s $a0, $fa0262; CHECK32-NEXT: andi $a0, $a0, 71263; CHECK32-NEXT: sltu $a0, $zero, $a0264; CHECK32-NEXT: ret265;266; CHECK64-LABEL: not_isfinite_d:267; CHECK64: # %bb.0: # %entry268; CHECK64-NEXT: fclass.d $fa0, $fa0269; CHECK64-NEXT: movfr2gr.d $a0, $fa0270; CHECK64-NEXT: andi $a0, $a0, 71271; CHECK64-NEXT: sltu $a0, $zero, $a0272; CHECK64-NEXT: ret273entry:274 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 519) ; ~0x1f8 = "~finite"275 ret i1 %0276}277 278define i1 @is_plus_finite_d(double %x) {279; CHECK32-LABEL: is_plus_finite_d:280; CHECK32: # %bb.0: # %entry281; CHECK32-NEXT: fclass.d $fa0, $fa0282; CHECK32-NEXT: movfr2gr.s $a0, $fa0283; CHECK32-NEXT: andi $a0, $a0, 896284; CHECK32-NEXT: sltu $a0, $zero, $a0285; CHECK32-NEXT: ret286;287; CHECK64-LABEL: is_plus_finite_d:288; CHECK64: # %bb.0: # %entry289; CHECK64-NEXT: fclass.d $fa0, $fa0290; CHECK64-NEXT: movfr2gr.d $a0, $fa0291; CHECK64-NEXT: andi $a0, $a0, 896292; CHECK64-NEXT: sltu $a0, $zero, $a0293; CHECK64-NEXT: ret294entry:295 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 448) ; 0x1c0 = "+finite"296 ret i1 %0297}298 299define i1 @not_is_plus_finite_d(double %x) {300; CHECK32-LABEL: not_is_plus_finite_d:301; CHECK32: # %bb.0: # %entry302; CHECK32-NEXT: fclass.d $fa0, $fa0303; CHECK32-NEXT: movfr2gr.s $a0, $fa0304; CHECK32-NEXT: andi $a0, $a0, 127305; CHECK32-NEXT: sltu $a0, $zero, $a0306; CHECK32-NEXT: ret307;308; CHECK64-LABEL: not_is_plus_finite_d:309; CHECK64: # %bb.0: # %entry310; CHECK64-NEXT: fclass.d $fa0, $fa0311; CHECK64-NEXT: movfr2gr.d $a0, $fa0312; CHECK64-NEXT: andi $a0, $a0, 127313; CHECK64-NEXT: sltu $a0, $zero, $a0314; CHECK64-NEXT: ret315entry:316 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 575) ; ~0x1c0 = ~"+finite"317 ret i1 %0318}319 320define i1 @is_minus_finite_d(double %x) {321; CHECK32-LABEL: is_minus_finite_d:322; CHECK32: # %bb.0: # %entry323; CHECK32-NEXT: fclass.d $fa0, $fa0324; CHECK32-NEXT: movfr2gr.s $a0, $fa0325; CHECK32-NEXT: andi $a0, $a0, 56326; CHECK32-NEXT: sltu $a0, $zero, $a0327; CHECK32-NEXT: ret328;329; CHECK64-LABEL: is_minus_finite_d:330; CHECK64: # %bb.0: # %entry331; CHECK64-NEXT: fclass.d $fa0, $fa0332; CHECK64-NEXT: movfr2gr.d $a0, $fa0333; CHECK64-NEXT: andi $a0, $a0, 56334; CHECK64-NEXT: sltu $a0, $zero, $a0335; CHECK64-NEXT: ret336entry:337 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 56) ; 0x38 = "-finite"338 ret i1 %0339}340 341define i1 @not_is_minus_finite_d(double %x) {342; CHECK32-LABEL: not_is_minus_finite_d:343; CHECK32: # %bb.0: # %entry344; CHECK32-NEXT: fclass.d $fa0, $fa0345; CHECK32-NEXT: movfr2gr.s $a0, $fa0346; CHECK32-NEXT: andi $a0, $a0, 967347; CHECK32-NEXT: sltu $a0, $zero, $a0348; CHECK32-NEXT: ret349;350; CHECK64-LABEL: not_is_minus_finite_d:351; CHECK64: # %bb.0: # %entry352; CHECK64-NEXT: fclass.d $fa0, $fa0353; CHECK64-NEXT: movfr2gr.d $a0, $fa0354; CHECK64-NEXT: andi $a0, $a0, 967355; CHECK64-NEXT: sltu $a0, $zero, $a0356; CHECK64-NEXT: ret357entry:358 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 967) ; ~0x38 = ~"-finite"359 ret i1 %0360}361 362define i1 @isnormal_d(double %x) {363; CHECK32-LABEL: isnormal_d:364; CHECK32: # %bb.0: # %entry365; CHECK32-NEXT: fclass.d $fa0, $fa0366; CHECK32-NEXT: movfr2gr.s $a0, $fa0367; CHECK32-NEXT: andi $a0, $a0, 136368; CHECK32-NEXT: sltu $a0, $zero, $a0369; CHECK32-NEXT: ret370;371; CHECK64-LABEL: isnormal_d:372; CHECK64: # %bb.0: # %entry373; CHECK64-NEXT: fclass.d $fa0, $fa0374; CHECK64-NEXT: movfr2gr.d $a0, $fa0375; CHECK64-NEXT: andi $a0, $a0, 136376; CHECK64-NEXT: sltu $a0, $zero, $a0377; CHECK64-NEXT: ret378entry:379 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 264) ; 0x108 = "normal"380 ret i1 %0381}382 383define i1 @not_isnormal_d(double %x) {384; CHECK32-LABEL: not_isnormal_d:385; CHECK32: # %bb.0: # %entry386; CHECK32-NEXT: fclass.d $fa0, $fa0387; CHECK32-NEXT: movfr2gr.s $a0, $fa0388; CHECK32-NEXT: andi $a0, $a0, 887389; CHECK32-NEXT: sltu $a0, $zero, $a0390; CHECK32-NEXT: ret391;392; CHECK64-LABEL: not_isnormal_d:393; CHECK64: # %bb.0: # %entry394; CHECK64-NEXT: fclass.d $fa0, $fa0395; CHECK64-NEXT: movfr2gr.d $a0, $fa0396; CHECK64-NEXT: andi $a0, $a0, 887397; CHECK64-NEXT: sltu $a0, $zero, $a0398; CHECK64-NEXT: ret399entry:400 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 759) ; ~0x108 = "~normal"401 ret i1 %0402}403 404define i1 @is_plus_normal_d(double %x) {405; CHECK32-LABEL: is_plus_normal_d:406; CHECK32: # %bb.0: # %entry407; CHECK32-NEXT: fclass.d $fa0, $fa0408; CHECK32-NEXT: movfr2gr.s $a0, $fa0409; CHECK32-NEXT: andi $a0, $a0, 128410; CHECK32-NEXT: sltu $a0, $zero, $a0411; CHECK32-NEXT: ret412;413; CHECK64-LABEL: is_plus_normal_d:414; CHECK64: # %bb.0: # %entry415; CHECK64-NEXT: fclass.d $fa0, $fa0416; CHECK64-NEXT: movfr2gr.d $a0, $fa0417; CHECK64-NEXT: andi $a0, $a0, 128418; CHECK64-NEXT: sltu $a0, $zero, $a0419; CHECK64-NEXT: ret420entry:421 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 256) ; 0x100 = "+normal"422 ret i1 %0423}424 425define i1 @issubnormal_d(double %x) {426; CHECK32-LABEL: issubnormal_d:427; CHECK32: # %bb.0: # %entry428; CHECK32-NEXT: fclass.d $fa0, $fa0429; CHECK32-NEXT: movfr2gr.s $a0, $fa0430; CHECK32-NEXT: andi $a0, $a0, 272431; CHECK32-NEXT: sltu $a0, $zero, $a0432; CHECK32-NEXT: ret433;434; CHECK64-LABEL: issubnormal_d:435; CHECK64: # %bb.0: # %entry436; CHECK64-NEXT: fclass.d $fa0, $fa0437; CHECK64-NEXT: movfr2gr.d $a0, $fa0438; CHECK64-NEXT: andi $a0, $a0, 272439; CHECK64-NEXT: sltu $a0, $zero, $a0440; CHECK64-NEXT: ret441entry:442 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 144) ; 0x90 = "subnormal"443 ret i1 %0444}445 446define i1 @not_issubnormal_d(double %x) {447; CHECK32-LABEL: not_issubnormal_d:448; CHECK32: # %bb.0: # %entry449; CHECK32-NEXT: fclass.d $fa0, $fa0450; CHECK32-NEXT: movfr2gr.s $a0, $fa0451; CHECK32-NEXT: andi $a0, $a0, 751452; CHECK32-NEXT: sltu $a0, $zero, $a0453; CHECK32-NEXT: ret454;455; CHECK64-LABEL: not_issubnormal_d:456; CHECK64: # %bb.0: # %entry457; CHECK64-NEXT: fclass.d $fa0, $fa0458; CHECK64-NEXT: movfr2gr.d $a0, $fa0459; CHECK64-NEXT: andi $a0, $a0, 751460; CHECK64-NEXT: sltu $a0, $zero, $a0461; CHECK64-NEXT: ret462entry:463 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 879) ; ~0x90 = "~subnormal"464 ret i1 %0465}466 467define i1 @is_plus_subnormal_d(double %x) {468; CHECK32-LABEL: is_plus_subnormal_d:469; CHECK32: # %bb.0: # %entry470; CHECK32-NEXT: fclass.d $fa0, $fa0471; CHECK32-NEXT: movfr2gr.s $a0, $fa0472; CHECK32-NEXT: andi $a0, $a0, 256473; CHECK32-NEXT: sltu $a0, $zero, $a0474; CHECK32-NEXT: ret475;476; CHECK64-LABEL: is_plus_subnormal_d:477; CHECK64: # %bb.0: # %entry478; CHECK64-NEXT: fclass.d $fa0, $fa0479; CHECK64-NEXT: movfr2gr.d $a0, $fa0480; CHECK64-NEXT: andi $a0, $a0, 256481; CHECK64-NEXT: sltu $a0, $zero, $a0482; CHECK64-NEXT: ret483entry:484 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 128) ; 0x80 = "+subnormal"485 ret i1 %0486}487 488define i1 @not_is_plus_subnormal_d(double %x) {489; CHECK32-LABEL: not_is_plus_subnormal_d:490; CHECK32: # %bb.0: # %entry491; CHECK32-NEXT: fclass.d $fa0, $fa0492; CHECK32-NEXT: movfr2gr.s $a0, $fa0493; CHECK32-NEXT: andi $a0, $a0, 767494; CHECK32-NEXT: sltu $a0, $zero, $a0495; CHECK32-NEXT: ret496;497; CHECK64-LABEL: not_is_plus_subnormal_d:498; CHECK64: # %bb.0: # %entry499; CHECK64-NEXT: fclass.d $fa0, $fa0500; CHECK64-NEXT: movfr2gr.d $a0, $fa0501; CHECK64-NEXT: andi $a0, $a0, 767502; CHECK64-NEXT: sltu $a0, $zero, $a0503; CHECK64-NEXT: ret504entry:505 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 895) ; ~0x80 = ~"+subnormal"506 ret i1 %0507}508 509define i1 @is_minus_subnormal_d(double %x) {510; CHECK32-LABEL: is_minus_subnormal_d:511; CHECK32: # %bb.0: # %entry512; CHECK32-NEXT: fclass.d $fa0, $fa0513; CHECK32-NEXT: movfr2gr.s $a0, $fa0514; CHECK32-NEXT: andi $a0, $a0, 16515; CHECK32-NEXT: sltu $a0, $zero, $a0516; CHECK32-NEXT: ret517;518; CHECK64-LABEL: is_minus_subnormal_d:519; CHECK64: # %bb.0: # %entry520; CHECK64-NEXT: fclass.d $fa0, $fa0521; CHECK64-NEXT: movfr2gr.d $a0, $fa0522; CHECK64-NEXT: andi $a0, $a0, 16523; CHECK64-NEXT: sltu $a0, $zero, $a0524; CHECK64-NEXT: ret525entry:526 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 16) ; 0x10 = "-subnormal"527 ret i1 %0528}529 530define i1 @not_is_minus_subnormal_d(double %x) {531; CHECK32-LABEL: not_is_minus_subnormal_d:532; CHECK32: # %bb.0: # %entry533; CHECK32-NEXT: fclass.d $fa0, $fa0534; CHECK32-NEXT: movfr2gr.s $a0, $fa0535; CHECK32-NEXT: andi $a0, $a0, 1007536; CHECK32-NEXT: sltu $a0, $zero, $a0537; CHECK32-NEXT: ret538;539; CHECK64-LABEL: not_is_minus_subnormal_d:540; CHECK64: # %bb.0: # %entry541; CHECK64-NEXT: fclass.d $fa0, $fa0542; CHECK64-NEXT: movfr2gr.d $a0, $fa0543; CHECK64-NEXT: andi $a0, $a0, 1007544; CHECK64-NEXT: sltu $a0, $zero, $a0545; CHECK64-NEXT: ret546entry:547 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1007) ; ~0x10 = ~"-subnormal"548 ret i1 %0549}550 551define i1 @iszero_d(double %x) {552; CHECK32-LABEL: iszero_d:553; CHECK32: # %bb.0: # %entry554; CHECK32-NEXT: fclass.d $fa0, $fa0555; CHECK32-NEXT: movfr2gr.s $a0, $fa0556; CHECK32-NEXT: andi $a0, $a0, 544557; CHECK32-NEXT: sltu $a0, $zero, $a0558; CHECK32-NEXT: ret559;560; CHECK64-LABEL: iszero_d:561; CHECK64: # %bb.0: # %entry562; CHECK64-NEXT: fclass.d $fa0, $fa0563; CHECK64-NEXT: movfr2gr.d $a0, $fa0564; CHECK64-NEXT: andi $a0, $a0, 544565; CHECK64-NEXT: sltu $a0, $zero, $a0566; CHECK64-NEXT: ret567entry:568 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) ; 0x60 = "zero"569 ret i1 %0570}571 572define i1 @not_iszero_d(double %x) {573; CHECK32-LABEL: not_iszero_d:574; CHECK32: # %bb.0: # %entry575; CHECK32-NEXT: fclass.d $fa0, $fa0576; CHECK32-NEXT: movfr2gr.s $a0, $fa0577; CHECK32-NEXT: andi $a0, $a0, 479578; CHECK32-NEXT: sltu $a0, $zero, $a0579; CHECK32-NEXT: ret580;581; CHECK64-LABEL: not_iszero_d:582; CHECK64: # %bb.0: # %entry583; CHECK64-NEXT: fclass.d $fa0, $fa0584; CHECK64-NEXT: movfr2gr.d $a0, $fa0585; CHECK64-NEXT: andi $a0, $a0, 479586; CHECK64-NEXT: sltu $a0, $zero, $a0587; CHECK64-NEXT: ret588entry:589 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 927) ; ~0x60 = "~zero"590 ret i1 %0591}592 593define i1 @issubnormal_or_zero_d(double %x) {594; CHECK32-LABEL: issubnormal_or_zero_d:595; CHECK32: # %bb.0: # %entry596; CHECK32-NEXT: fclass.d $fa0, $fa0597; CHECK32-NEXT: movfr2gr.s $a0, $fa0598; CHECK32-NEXT: andi $a0, $a0, 816599; CHECK32-NEXT: sltu $a0, $zero, $a0600; CHECK32-NEXT: ret601;602; CHECK64-LABEL: issubnormal_or_zero_d:603; CHECK64: # %bb.0: # %entry604; CHECK64-NEXT: fclass.d $fa0, $fa0605; CHECK64-NEXT: movfr2gr.d $a0, $fa0606; CHECK64-NEXT: andi $a0, $a0, 816607; CHECK64-NEXT: sltu $a0, $zero, $a0608; CHECK64-NEXT: ret609entry:610 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 240) ; 0xf0 = "subnormal|zero"611 ret i1 %0612}613 614define i1 @not_issubnormal_or_zero_d(double %x) {615; CHECK32-LABEL: not_issubnormal_or_zero_d:616; CHECK32: # %bb.0: # %entry617; CHECK32-NEXT: fclass.d $fa0, $fa0618; CHECK32-NEXT: movfr2gr.s $a0, $fa0619; CHECK32-NEXT: andi $a0, $a0, 207620; CHECK32-NEXT: sltu $a0, $zero, $a0621; CHECK32-NEXT: ret622;623; CHECK64-LABEL: not_issubnormal_or_zero_d:624; CHECK64: # %bb.0: # %entry625; CHECK64-NEXT: fclass.d $fa0, $fa0626; CHECK64-NEXT: movfr2gr.d $a0, $fa0627; CHECK64-NEXT: andi $a0, $a0, 207628; CHECK64-NEXT: sltu $a0, $zero, $a0629; CHECK64-NEXT: ret630entry:631 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"632 ret i1 %0633}634 635define i1 @is_plus_zero_d(double %x) {636; CHECK32-LABEL: is_plus_zero_d:637; CHECK32: # %bb.0: # %entry638; CHECK32-NEXT: fclass.d $fa0, $fa0639; CHECK32-NEXT: movfr2gr.s $a0, $fa0640; CHECK32-NEXT: andi $a0, $a0, 512641; CHECK32-NEXT: sltu $a0, $zero, $a0642; CHECK32-NEXT: ret643;644; CHECK64-LABEL: is_plus_zero_d:645; CHECK64: # %bb.0: # %entry646; CHECK64-NEXT: fclass.d $fa0, $fa0647; CHECK64-NEXT: movfr2gr.d $a0, $fa0648; CHECK64-NEXT: andi $a0, $a0, 512649; CHECK64-NEXT: sltu $a0, $zero, $a0650; CHECK64-NEXT: ret651entry:652 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 64) ; 0x40 = "+zero"653 ret i1 %0654}655 656define i1 @not_is_plus_zero_d(double %x) {657; CHECK32-LABEL: not_is_plus_zero_d:658; CHECK32: # %bb.0: # %entry659; CHECK32-NEXT: fclass.d $fa0, $fa0660; CHECK32-NEXT: movfr2gr.s $a0, $fa0661; CHECK32-NEXT: andi $a0, $a0, 511662; CHECK32-NEXT: sltu $a0, $zero, $a0663; CHECK32-NEXT: ret664;665; CHECK64-LABEL: not_is_plus_zero_d:666; CHECK64: # %bb.0: # %entry667; CHECK64-NEXT: fclass.d $fa0, $fa0668; CHECK64-NEXT: movfr2gr.d $a0, $fa0669; CHECK64-NEXT: andi $a0, $a0, 511670; CHECK64-NEXT: sltu $a0, $zero, $a0671; CHECK64-NEXT: ret672entry:673 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 959) ; ~0x40 = ~"+zero"674 ret i1 %0675}676 677define i1 @is_minus_zero_d(double %x) {678; CHECK32-LABEL: is_minus_zero_d:679; CHECK32: # %bb.0: # %entry680; CHECK32-NEXT: fclass.d $fa0, $fa0681; CHECK32-NEXT: movfr2gr.s $a0, $fa0682; CHECK32-NEXT: andi $a0, $a0, 32683; CHECK32-NEXT: sltu $a0, $zero, $a0684; CHECK32-NEXT: ret685;686; CHECK64-LABEL: is_minus_zero_d:687; CHECK64: # %bb.0: # %entry688; CHECK64-NEXT: fclass.d $fa0, $fa0689; CHECK64-NEXT: movfr2gr.d $a0, $fa0690; CHECK64-NEXT: andi $a0, $a0, 32691; CHECK64-NEXT: sltu $a0, $zero, $a0692; CHECK64-NEXT: ret693entry:694 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 32) ; 0x20 = "-zero"695 ret i1 %0696}697 698define i1 @not_is_minus_zero_d(double %x) {699; CHECK32-LABEL: not_is_minus_zero_d:700; CHECK32: # %bb.0: # %entry701; CHECK32-NEXT: fclass.d $fa0, $fa0702; CHECK32-NEXT: movfr2gr.s $a0, $fa0703; CHECK32-NEXT: andi $a0, $a0, 991704; CHECK32-NEXT: sltu $a0, $zero, $a0705; CHECK32-NEXT: ret706;707; CHECK64-LABEL: not_is_minus_zero_d:708; CHECK64: # %bb.0: # %entry709; CHECK64-NEXT: fclass.d $fa0, $fa0710; CHECK64-NEXT: movfr2gr.d $a0, $fa0711; CHECK64-NEXT: andi $a0, $a0, 991712; CHECK64-NEXT: sltu $a0, $zero, $a0713; CHECK64-NEXT: ret714entry:715 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 991) ; ~0x20 = ~"-zero"716 ret i1 %0717}718 719define i1 @isnone_d(double %x) {720; CHECK32-LABEL: isnone_d:721; CHECK32: # %bb.0: # %entry722; CHECK32-NEXT: fclass.d $fa0, $fa0723; CHECK32-NEXT: movfr2gr.s $a0, $fa0724; CHECK32-NEXT: andi $a0, $a0, 0725; CHECK32-NEXT: sltu $a0, $zero, $a0726; CHECK32-NEXT: ret727;728; CHECK64-LABEL: isnone_d:729; CHECK64: # %bb.0: # %entry730; CHECK64-NEXT: fclass.d $fa0, $fa0731; CHECK64-NEXT: movfr2gr.d $a0, $fa0732; CHECK64-NEXT: andi $a0, $a0, 0733; CHECK64-NEXT: sltu $a0, $zero, $a0734; CHECK64-NEXT: ret735entry:736 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 0)737 ret i1 %0738}739 740define i1 @isany_d(double %x) {741; CHECK32-LABEL: isany_d:742; CHECK32: # %bb.0: # %entry743; CHECK32-NEXT: fclass.d $fa0, $fa0744; CHECK32-NEXT: movfr2gr.s $a0, $fa0745; CHECK32-NEXT: andi $a0, $a0, 1023746; CHECK32-NEXT: sltu $a0, $zero, $a0747; CHECK32-NEXT: ret748;749; CHECK64-LABEL: isany_d:750; CHECK64: # %bb.0: # %entry751; CHECK64-NEXT: fclass.d $fa0, $fa0752; CHECK64-NEXT: movfr2gr.d $a0, $fa0753; CHECK64-NEXT: andi $a0, $a0, 1023754; CHECK64-NEXT: sltu $a0, $zero, $a0755; CHECK64-NEXT: ret756entry:757 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1023)758 ret i1 %0759}760 761define i1 @iszero_or_nan_d(double %x) {762; CHECK32-LABEL: iszero_or_nan_d:763; CHECK32: # %bb.0: # %entry764; CHECK32-NEXT: fclass.d $fa0, $fa0765; CHECK32-NEXT: movfr2gr.s $a0, $fa0766; CHECK32-NEXT: andi $a0, $a0, 547767; CHECK32-NEXT: sltu $a0, $zero, $a0768; CHECK32-NEXT: ret769;770; CHECK64-LABEL: iszero_or_nan_d:771; CHECK64: # %bb.0: # %entry772; CHECK64-NEXT: fclass.d $fa0, $fa0773; CHECK64-NEXT: movfr2gr.d $a0, $fa0774; CHECK64-NEXT: andi $a0, $a0, 547775; CHECK64-NEXT: sltu $a0, $zero, $a0776; CHECK64-NEXT: ret777entry:778 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 99) ; 0x60|0x3 = "zero|nan"779 ret i1 %0780}781 782define i1 @not_iszero_or_nan_d(double %x) {783; CHECK32-LABEL: not_iszero_or_nan_d:784; CHECK32: # %bb.0: # %entry785; CHECK32-NEXT: fclass.d $fa0, $fa0786; CHECK32-NEXT: movfr2gr.s $a0, $fa0787; CHECK32-NEXT: andi $a0, $a0, 476788; CHECK32-NEXT: sltu $a0, $zero, $a0789; CHECK32-NEXT: ret790;791; CHECK64-LABEL: not_iszero_or_nan_d:792; CHECK64: # %bb.0: # %entry793; CHECK64-NEXT: fclass.d $fa0, $fa0794; CHECK64-NEXT: movfr2gr.d $a0, $fa0795; CHECK64-NEXT: andi $a0, $a0, 476796; CHECK64-NEXT: sltu $a0, $zero, $a0797; CHECK64-NEXT: ret798entry:799 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 924) ; ~0x60 = "~(zero|nan)"800 ret i1 %0801}802 803define i1 @iszero_or_qnan_d(double %x) {804; CHECK32-LABEL: iszero_or_qnan_d:805; CHECK32: # %bb.0: # %entry806; CHECK32-NEXT: fclass.d $fa0, $fa0807; CHECK32-NEXT: movfr2gr.s $a0, $fa0808; CHECK32-NEXT: andi $a0, $a0, 546809; CHECK32-NEXT: sltu $a0, $zero, $a0810; CHECK32-NEXT: ret811;812; CHECK64-LABEL: iszero_or_qnan_d:813; CHECK64: # %bb.0: # %entry814; CHECK64-NEXT: fclass.d $fa0, $fa0815; CHECK64-NEXT: movfr2gr.d $a0, $fa0816; CHECK64-NEXT: andi $a0, $a0, 546817; CHECK64-NEXT: sltu $a0, $zero, $a0818; CHECK64-NEXT: ret819entry:820 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 98) ; 0x60|0x2 = "zero|qnan"821 ret i1 %0822}823 824define i1 @iszero_or_snan_d(double %x) {825; CHECK32-LABEL: iszero_or_snan_d:826; CHECK32: # %bb.0: # %entry827; CHECK32-NEXT: fclass.d $fa0, $fa0828; CHECK32-NEXT: movfr2gr.s $a0, $fa0829; CHECK32-NEXT: andi $a0, $a0, 545830; CHECK32-NEXT: sltu $a0, $zero, $a0831; CHECK32-NEXT: ret832;833; CHECK64-LABEL: iszero_or_snan_d:834; CHECK64: # %bb.0: # %entry835; CHECK64-NEXT: fclass.d $fa0, $fa0836; CHECK64-NEXT: movfr2gr.d $a0, $fa0837; CHECK64-NEXT: andi $a0, $a0, 545838; CHECK64-NEXT: sltu $a0, $zero, $a0839; CHECK64-NEXT: ret840entry:841 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 97) ; 0x60|0x1 = "zero|snan"842 ret i1 %0843}844 845define i1 @not_iszero_or_qnan_d(double %x) {846; CHECK32-LABEL: not_iszero_or_qnan_d:847; CHECK32: # %bb.0: # %entry848; CHECK32-NEXT: fclass.d $fa0, $fa0849; CHECK32-NEXT: movfr2gr.s $a0, $fa0850; CHECK32-NEXT: andi $a0, $a0, 477851; CHECK32-NEXT: sltu $a0, $zero, $a0852; CHECK32-NEXT: ret853;854; CHECK64-LABEL: not_iszero_or_qnan_d:855; CHECK64: # %bb.0: # %entry856; CHECK64-NEXT: fclass.d $fa0, $fa0857; CHECK64-NEXT: movfr2gr.d $a0, $fa0858; CHECK64-NEXT: andi $a0, $a0, 477859; CHECK64-NEXT: sltu $a0, $zero, $a0860; CHECK64-NEXT: ret861entry:862 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 925) ; ~(0x60|0x2) = "~(zero|qnan)"863 ret i1 %0864}865 866define i1 @not_iszero_or_snan_d(double %x) {867; CHECK32-LABEL: not_iszero_or_snan_d:868; CHECK32: # %bb.0: # %entry869; CHECK32-NEXT: fclass.d $fa0, $fa0870; CHECK32-NEXT: movfr2gr.s $a0, $fa0871; CHECK32-NEXT: andi $a0, $a0, 478872; CHECK32-NEXT: sltu $a0, $zero, $a0873; CHECK32-NEXT: ret874;875; CHECK64-LABEL: not_iszero_or_snan_d:876; CHECK64: # %bb.0: # %entry877; CHECK64-NEXT: fclass.d $fa0, $fa0878; CHECK64-NEXT: movfr2gr.d $a0, $fa0879; CHECK64-NEXT: andi $a0, $a0, 478880; CHECK64-NEXT: sltu $a0, $zero, $a0881; CHECK64-NEXT: ret882entry:883 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 926) ; ~(0x60|0x1) = "~(zero|snan)"884 ret i1 %0885}886 887define i1 @isinf_or_nan_d(double %x) {888; CHECK32-LABEL: isinf_or_nan_d:889; CHECK32: # %bb.0: # %entry890; CHECK32-NEXT: fclass.d $fa0, $fa0891; CHECK32-NEXT: movfr2gr.s $a0, $fa0892; CHECK32-NEXT: andi $a0, $a0, 71893; CHECK32-NEXT: sltu $a0, $zero, $a0894; CHECK32-NEXT: ret895;896; CHECK64-LABEL: isinf_or_nan_d:897; CHECK64: # %bb.0: # %entry898; CHECK64-NEXT: fclass.d $fa0, $fa0899; CHECK64-NEXT: movfr2gr.d $a0, $fa0900; CHECK64-NEXT: andi $a0, $a0, 71901; CHECK64-NEXT: sltu $a0, $zero, $a0902; CHECK64-NEXT: ret903entry:904 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 519) ; 0x204|0x3 = "inf|nan"905 ret i1 %0906}907 908define i1 @not_isinf_or_nan_d(double %x) {909; CHECK32-LABEL: not_isinf_or_nan_d:910; CHECK32: # %bb.0: # %entry911; CHECK32-NEXT: fclass.d $fa0, $fa0912; CHECK32-NEXT: movfr2gr.s $a0, $fa0913; CHECK32-NEXT: andi $a0, $a0, 952914; CHECK32-NEXT: sltu $a0, $zero, $a0915; CHECK32-NEXT: ret916;917; CHECK64-LABEL: not_isinf_or_nan_d:918; CHECK64: # %bb.0: # %entry919; CHECK64-NEXT: fclass.d $fa0, $fa0920; CHECK64-NEXT: movfr2gr.d $a0, $fa0921; CHECK64-NEXT: andi $a0, $a0, 952922; CHECK64-NEXT: sltu $a0, $zero, $a0923; CHECK64-NEXT: ret924entry:925 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"926 ret i1 %0927}928 929define i1 @isfinite_or_nan_d(double %x) {930; CHECK32-LABEL: isfinite_or_nan_d:931; CHECK32: # %bb.0: # %entry932; CHECK32-NEXT: fclass.d $fa0, $fa0933; CHECK32-NEXT: movfr2gr.s $a0, $fa0934; CHECK32-NEXT: andi $a0, $a0, 955935; CHECK32-NEXT: sltu $a0, $zero, $a0936; CHECK32-NEXT: ret937;938; CHECK64-LABEL: isfinite_or_nan_d:939; CHECK64: # %bb.0: # %entry940; CHECK64-NEXT: fclass.d $fa0, $fa0941; CHECK64-NEXT: movfr2gr.d $a0, $fa0942; CHECK64-NEXT: andi $a0, $a0, 955943; CHECK64-NEXT: sltu $a0, $zero, $a0944; CHECK64-NEXT: ret945entry:946 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 507) ; 0x1f8|0x3 = "finite|nan"947 ret i1 %0948}949 950define i1 @not_isfinite_or_nan_d(double %x) {951; CHECK32-LABEL: not_isfinite_or_nan_d:952; CHECK32: # %bb.0: # %entry953; CHECK32-NEXT: fclass.d $fa0, $fa0954; CHECK32-NEXT: movfr2gr.s $a0, $fa0955; CHECK32-NEXT: andi $a0, $a0, 68956; CHECK32-NEXT: sltu $a0, $zero, $a0957; CHECK32-NEXT: ret958;959; CHECK64-LABEL: not_isfinite_or_nan_d:960; CHECK64: # %bb.0: # %entry961; CHECK64-NEXT: fclass.d $fa0, $fa0962; CHECK64-NEXT: movfr2gr.d $a0, $fa0963; CHECK64-NEXT: andi $a0, $a0, 68964; CHECK64-NEXT: sltu $a0, $zero, $a0965; CHECK64-NEXT: ret966entry:967 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516) ; ~(0x1f8|0x3) = "~(finite|nan)"968 ret i1 %0969}970 971define i1 @is_plus_inf_or_nan_d(double %x) {972; CHECK32-LABEL: is_plus_inf_or_nan_d:973; CHECK32: # %bb.0:974; CHECK32-NEXT: fclass.d $fa0, $fa0975; CHECK32-NEXT: movfr2gr.s $a0, $fa0976; CHECK32-NEXT: andi $a0, $a0, 67977; CHECK32-NEXT: sltu $a0, $zero, $a0978; CHECK32-NEXT: ret979;980; CHECK64-LABEL: is_plus_inf_or_nan_d:981; CHECK64: # %bb.0:982; CHECK64-NEXT: fclass.d $fa0, $fa0983; CHECK64-NEXT: movfr2gr.d $a0, $fa0984; CHECK64-NEXT: andi $a0, $a0, 67985; CHECK64-NEXT: sltu $a0, $zero, $a0986; CHECK64-NEXT: ret987 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 515) ; 0x200|0x3 = "+inf|nan"988 ret i1 %class989}990 991define i1 @is_minus_inf_or_nan_d(double %x) {992; CHECK32-LABEL: is_minus_inf_or_nan_d:993; CHECK32: # %bb.0:994; CHECK32-NEXT: fclass.d $fa0, $fa0995; CHECK32-NEXT: movfr2gr.s $a0, $fa0996; CHECK32-NEXT: andi $a0, $a0, 7997; CHECK32-NEXT: sltu $a0, $zero, $a0998; CHECK32-NEXT: ret999;1000; CHECK64-LABEL: is_minus_inf_or_nan_d:1001; CHECK64: # %bb.0:1002; CHECK64-NEXT: fclass.d $fa0, $fa01003; CHECK64-NEXT: movfr2gr.d $a0, $fa01004; CHECK64-NEXT: andi $a0, $a0, 71005; CHECK64-NEXT: sltu $a0, $zero, $a01006; CHECK64-NEXT: ret1007 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 7) ; "-inf|nan"1008 ret i1 %class1009}1010 1011define i1 @not_is_plus_inf_or_nan_d(double %x) {1012; CHECK32-LABEL: not_is_plus_inf_or_nan_d:1013; CHECK32: # %bb.0:1014; CHECK32-NEXT: fclass.d $fa0, $fa01015; CHECK32-NEXT: movfr2gr.s $a0, $fa01016; CHECK32-NEXT: andi $a0, $a0, 9561017; CHECK32-NEXT: sltu $a0, $zero, $a01018; CHECK32-NEXT: ret1019;1020; CHECK64-LABEL: not_is_plus_inf_or_nan_d:1021; CHECK64: # %bb.0:1022; CHECK64-NEXT: fclass.d $fa0, $fa01023; CHECK64-NEXT: movfr2gr.d $a0, $fa01024; CHECK64-NEXT: andi $a0, $a0, 9561025; CHECK64-NEXT: sltu $a0, $zero, $a01026; CHECK64-NEXT: ret1027 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 508) ; ~(0x200|0x3) = "~(+inf|nan)"1028 ret i1 %class1029}1030 1031define i1 @not_is_minus_inf_or_nan_d(double %x) {1032; CHECK32-LABEL: not_is_minus_inf_or_nan_d:1033; CHECK32: # %bb.0:1034; CHECK32-NEXT: fclass.d $fa0, $fa01035; CHECK32-NEXT: movfr2gr.s $a0, $fa01036; CHECK32-NEXT: andi $a0, $a0, 10161037; CHECK32-NEXT: sltu $a0, $zero, $a01038; CHECK32-NEXT: ret1039;1040; CHECK64-LABEL: not_is_minus_inf_or_nan_d:1041; CHECK64: # %bb.0:1042; CHECK64-NEXT: fclass.d $fa0, $fa01043; CHECK64-NEXT: movfr2gr.d $a0, $fa01044; CHECK64-NEXT: andi $a0, $a0, 10161045; CHECK64-NEXT: sltu $a0, $zero, $a01046; CHECK64-NEXT: ret1047 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1016) ; "~(-inf|nan)"1048 ret i1 %class1049}1050 1051define i1 @is_plus_inf_or_snan_d(double %x) {1052; CHECK32-LABEL: is_plus_inf_or_snan_d:1053; CHECK32: # %bb.0:1054; CHECK32-NEXT: fclass.d $fa0, $fa01055; CHECK32-NEXT: movfr2gr.s $a0, $fa01056; CHECK32-NEXT: andi $a0, $a0, 651057; CHECK32-NEXT: sltu $a0, $zero, $a01058; CHECK32-NEXT: ret1059;1060; CHECK64-LABEL: is_plus_inf_or_snan_d:1061; CHECK64: # %bb.0:1062; CHECK64-NEXT: fclass.d $fa0, $fa01063; CHECK64-NEXT: movfr2gr.d $a0, $fa01064; CHECK64-NEXT: andi $a0, $a0, 651065; CHECK64-NEXT: sltu $a0, $zero, $a01066; CHECK64-NEXT: ret1067 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 513) ; 0x200|0x1 = "+inf|snan"1068 ret i1 %class1069}1070 1071define i1 @is_plus_inf_or_qnan_d(double %x) {1072; CHECK32-LABEL: is_plus_inf_or_qnan_d:1073; CHECK32: # %bb.0:1074; CHECK32-NEXT: fclass.d $fa0, $fa01075; CHECK32-NEXT: movfr2gr.s $a0, $fa01076; CHECK32-NEXT: andi $a0, $a0, 661077; CHECK32-NEXT: sltu $a0, $zero, $a01078; CHECK32-NEXT: ret1079;1080; CHECK64-LABEL: is_plus_inf_or_qnan_d:1081; CHECK64: # %bb.0:1082; CHECK64-NEXT: fclass.d $fa0, $fa01083; CHECK64-NEXT: movfr2gr.d $a0, $fa01084; CHECK64-NEXT: andi $a0, $a0, 661085; CHECK64-NEXT: sltu $a0, $zero, $a01086; CHECK64-NEXT: ret1087 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 514) ; 0x200|0x1 = "+inf|qnan"1088 ret i1 %class1089}1090 1091define i1 @not_is_plus_inf_or_snan_d(double %x) {1092; CHECK32-LABEL: not_is_plus_inf_or_snan_d:1093; CHECK32: # %bb.0:1094; CHECK32-NEXT: fclass.d $fa0, $fa01095; CHECK32-NEXT: movfr2gr.s $a0, $fa01096; CHECK32-NEXT: andi $a0, $a0, 9581097; CHECK32-NEXT: sltu $a0, $zero, $a01098; CHECK32-NEXT: ret1099;1100; CHECK64-LABEL: not_is_plus_inf_or_snan_d:1101; CHECK64: # %bb.0:1102; CHECK64-NEXT: fclass.d $fa0, $fa01103; CHECK64-NEXT: movfr2gr.d $a0, $fa01104; CHECK64-NEXT: andi $a0, $a0, 9581105; CHECK64-NEXT: sltu $a0, $zero, $a01106; CHECK64-NEXT: ret1107 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 510) ; ~(+inf|snan)1108 ret i1 %class1109}1110 1111define i1 @not_is_plus_inf_or_qnan_d(double %x) {1112; CHECK32-LABEL: not_is_plus_inf_or_qnan_d:1113; CHECK32: # %bb.0:1114; CHECK32-NEXT: fclass.d $fa0, $fa01115; CHECK32-NEXT: movfr2gr.s $a0, $fa01116; CHECK32-NEXT: andi $a0, $a0, 9571117; CHECK32-NEXT: sltu $a0, $zero, $a01118; CHECK32-NEXT: ret1119;1120; CHECK64-LABEL: not_is_plus_inf_or_qnan_d:1121; CHECK64: # %bb.0:1122; CHECK64-NEXT: fclass.d $fa0, $fa01123; CHECK64-NEXT: movfr2gr.d $a0, $fa01124; CHECK64-NEXT: andi $a0, $a0, 9571125; CHECK64-NEXT: sltu $a0, $zero, $a01126; CHECK64-NEXT: ret1127 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 509) ; ~(+inf|qnan)1128 ret i1 %class1129}1130 1131define i1 @is_minus_inf_or_snan_d(double %x) {1132; CHECK32-LABEL: is_minus_inf_or_snan_d:1133; CHECK32: # %bb.0:1134; CHECK32-NEXT: fclass.d $fa0, $fa01135; CHECK32-NEXT: movfr2gr.s $a0, $fa01136; CHECK32-NEXT: andi $a0, $a0, 51137; CHECK32-NEXT: sltu $a0, $zero, $a01138; CHECK32-NEXT: ret1139;1140; CHECK64-LABEL: is_minus_inf_or_snan_d:1141; CHECK64: # %bb.0:1142; CHECK64-NEXT: fclass.d $fa0, $fa01143; CHECK64-NEXT: movfr2gr.d $a0, $fa01144; CHECK64-NEXT: andi $a0, $a0, 51145; CHECK64-NEXT: sltu $a0, $zero, $a01146; CHECK64-NEXT: ret1147 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 5) ; "-inf|snan"1148 ret i1 %class1149}1150 1151define i1 @is_minus_inf_or_qnan_d(double %x) {1152; CHECK32-LABEL: is_minus_inf_or_qnan_d:1153; CHECK32: # %bb.0:1154; CHECK32-NEXT: fclass.d $fa0, $fa01155; CHECK32-NEXT: movfr2gr.s $a0, $fa01156; CHECK32-NEXT: andi $a0, $a0, 61157; CHECK32-NEXT: sltu $a0, $zero, $a01158; CHECK32-NEXT: ret1159;1160; CHECK64-LABEL: is_minus_inf_or_qnan_d:1161; CHECK64: # %bb.0:1162; CHECK64-NEXT: fclass.d $fa0, $fa01163; CHECK64-NEXT: movfr2gr.d $a0, $fa01164; CHECK64-NEXT: andi $a0, $a0, 61165; CHECK64-NEXT: sltu $a0, $zero, $a01166; CHECK64-NEXT: ret1167 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 6) ; "-inf|qnan"1168 ret i1 %class1169}1170 1171define i1 @not_is_minus_inf_or_snan_d(double %x) {1172; CHECK32-LABEL: not_is_minus_inf_or_snan_d:1173; CHECK32: # %bb.0:1174; CHECK32-NEXT: fclass.d $fa0, $fa01175; CHECK32-NEXT: movfr2gr.s $a0, $fa01176; CHECK32-NEXT: andi $a0, $a0, 10181177; CHECK32-NEXT: sltu $a0, $zero, $a01178; CHECK32-NEXT: ret1179;1180; CHECK64-LABEL: not_is_minus_inf_or_snan_d:1181; CHECK64: # %bb.0:1182; CHECK64-NEXT: fclass.d $fa0, $fa01183; CHECK64-NEXT: movfr2gr.d $a0, $fa01184; CHECK64-NEXT: andi $a0, $a0, 10181185; CHECK64-NEXT: sltu $a0, $zero, $a01186; CHECK64-NEXT: ret1187 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1018) ; "~(-inf|snan)"1188 ret i1 %class1189}1190 1191define i1 @not_is_minus_inf_or_qnan_d(double %x) {1192; CHECK32-LABEL: not_is_minus_inf_or_qnan_d:1193; CHECK32: # %bb.0:1194; CHECK32-NEXT: fclass.d $fa0, $fa01195; CHECK32-NEXT: movfr2gr.s $a0, $fa01196; CHECK32-NEXT: andi $a0, $a0, 10171197; CHECK32-NEXT: sltu $a0, $zero, $a01198; CHECK32-NEXT: ret1199;1200; CHECK64-LABEL: not_is_minus_inf_or_qnan_d:1201; CHECK64: # %bb.0:1202; CHECK64-NEXT: fclass.d $fa0, $fa01203; CHECK64-NEXT: movfr2gr.d $a0, $fa01204; CHECK64-NEXT: andi $a0, $a0, 10171205; CHECK64-NEXT: sltu $a0, $zero, $a01206; CHECK64-NEXT: ret1207 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1017) ; "-inf|qnan"1208 ret i1 %class1209}1210 1211define i1 @issubnormal_or_nan_d(double %x) {1212; CHECK32-LABEL: issubnormal_or_nan_d:1213; CHECK32: # %bb.0:1214; CHECK32-NEXT: fclass.d $fa0, $fa01215; CHECK32-NEXT: movfr2gr.s $a0, $fa01216; CHECK32-NEXT: andi $a0, $a0, 2751217; CHECK32-NEXT: sltu $a0, $zero, $a01218; CHECK32-NEXT: ret1219;1220; CHECK64-LABEL: issubnormal_or_nan_d:1221; CHECK64: # %bb.0:1222; CHECK64-NEXT: fclass.d $fa0, $fa01223; CHECK64-NEXT: movfr2gr.d $a0, $fa01224; CHECK64-NEXT: andi $a0, $a0, 2751225; CHECK64-NEXT: sltu $a0, $zero, $a01226; CHECK64-NEXT: ret1227 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 147) ; 0x90|0x3 = "subnormal|nan"1228 ret i1 %class1229}1230 1231define i1 @issubnormal_or_zero_or_nan_d(double %x) {1232; CHECK32-LABEL: issubnormal_or_zero_or_nan_d:1233; CHECK32: # %bb.0:1234; CHECK32-NEXT: fclass.d $fa0, $fa01235; CHECK32-NEXT: movfr2gr.s $a0, $fa01236; CHECK32-NEXT: andi $a0, $a0, 8191237; CHECK32-NEXT: sltu $a0, $zero, $a01238; CHECK32-NEXT: ret1239;1240; CHECK64-LABEL: issubnormal_or_zero_or_nan_d:1241; CHECK64: # %bb.0:1242; CHECK64-NEXT: fclass.d $fa0, $fa01243; CHECK64-NEXT: movfr2gr.d $a0, $fa01244; CHECK64-NEXT: andi $a0, $a0, 8191245; CHECK64-NEXT: sltu $a0, $zero, $a01246; CHECK64-NEXT: ret1247 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"1248 ret i1 %class1249}1250 1251define i1 @issubnormal_or_zero_or_snan_d(double %x) {1252; CHECK32-LABEL: issubnormal_or_zero_or_snan_d:1253; CHECK32: # %bb.0:1254; CHECK32-NEXT: fclass.d $fa0, $fa01255; CHECK32-NEXT: movfr2gr.s $a0, $fa01256; CHECK32-NEXT: andi $a0, $a0, 8171257; CHECK32-NEXT: sltu $a0, $zero, $a01258; CHECK32-NEXT: ret1259;1260; CHECK64-LABEL: issubnormal_or_zero_or_snan_d:1261; CHECK64: # %bb.0:1262; CHECK64-NEXT: fclass.d $fa0, $fa01263; CHECK64-NEXT: movfr2gr.d $a0, $fa01264; CHECK64-NEXT: andi $a0, $a0, 8171265; CHECK64-NEXT: sltu $a0, $zero, $a01266; CHECK64-NEXT: ret1267 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 241) ; 0x90|0x1 = "subnormal|snan"1268 ret i1 %class1269}1270 1271define i1 @issubnormal_or_zero_or_qnan_d(double %x) {1272; CHECK32-LABEL: issubnormal_or_zero_or_qnan_d:1273; CHECK32: # %bb.0:1274; CHECK32-NEXT: fclass.d $fa0, $fa01275; CHECK32-NEXT: movfr2gr.s $a0, $fa01276; CHECK32-NEXT: andi $a0, $a0, 8181277; CHECK32-NEXT: sltu $a0, $zero, $a01278; CHECK32-NEXT: ret1279;1280; CHECK64-LABEL: issubnormal_or_zero_or_qnan_d:1281; CHECK64: # %bb.0:1282; CHECK64-NEXT: fclass.d $fa0, $fa01283; CHECK64-NEXT: movfr2gr.d $a0, $fa01284; CHECK64-NEXT: andi $a0, $a0, 8181285; CHECK64-NEXT: sltu $a0, $zero, $a01286; CHECK64-NEXT: ret1287 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 242) ; 0x90|0x2 = "subnormal|qnan"1288 ret i1 %class1289}1290 1291define i1 @not_issubnormal_or_nan_d(double %x) {1292; CHECK32-LABEL: not_issubnormal_or_nan_d:1293; CHECK32: # %bb.0:1294; CHECK32-NEXT: fclass.d $fa0, $fa01295; CHECK32-NEXT: movfr2gr.s $a0, $fa01296; CHECK32-NEXT: andi $a0, $a0, 7481297; CHECK32-NEXT: sltu $a0, $zero, $a01298; CHECK32-NEXT: ret1299;1300; CHECK64-LABEL: not_issubnormal_or_nan_d:1301; CHECK64: # %bb.0:1302; CHECK64-NEXT: fclass.d $fa0, $fa01303; CHECK64-NEXT: movfr2gr.d $a0, $fa01304; CHECK64-NEXT: andi $a0, $a0, 7481305; CHECK64-NEXT: sltu $a0, $zero, $a01306; CHECK64-NEXT: ret1307 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 876) ; ~(0x90|0x3) = ~"subnormal|nan"1308 ret i1 %class1309}1310 1311define i1 @not_issubnormal_or_zero_or_nan_d(double %x) {1312; CHECK32-LABEL: not_issubnormal_or_zero_or_nan_d:1313; CHECK32: # %bb.0:1314; CHECK32-NEXT: fclass.d $fa0, $fa01315; CHECK32-NEXT: movfr2gr.s $a0, $fa01316; CHECK32-NEXT: andi $a0, $a0, 2041317; CHECK32-NEXT: sltu $a0, $zero, $a01318; CHECK32-NEXT: ret1319;1320; CHECK64-LABEL: not_issubnormal_or_zero_or_nan_d:1321; CHECK64: # %bb.0:1322; CHECK64-NEXT: fclass.d $fa0, $fa01323; CHECK64-NEXT: movfr2gr.d $a0, $fa01324; CHECK64-NEXT: andi $a0, $a0, 2041325; CHECK64-NEXT: sltu $a0, $zero, $a01326; CHECK64-NEXT: ret1327 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"1328 ret i1 %class1329}1330 1331define i1 @not_issubnormal_or_zero_or_snan_d(double %x) {1332; CHECK32-LABEL: not_issubnormal_or_zero_or_snan_d:1333; CHECK32: # %bb.0:1334; CHECK32-NEXT: fclass.d $fa0, $fa01335; CHECK32-NEXT: movfr2gr.s $a0, $fa01336; CHECK32-NEXT: andi $a0, $a0, 2061337; CHECK32-NEXT: sltu $a0, $zero, $a01338; CHECK32-NEXT: ret1339;1340; CHECK64-LABEL: not_issubnormal_or_zero_or_snan_d:1341; CHECK64: # %bb.0:1342; CHECK64-NEXT: fclass.d $fa0, $fa01343; CHECK64-NEXT: movfr2gr.d $a0, $fa01344; CHECK64-NEXT: andi $a0, $a0, 2061345; CHECK64-NEXT: sltu $a0, $zero, $a01346; CHECK64-NEXT: ret1347 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 782) ; ~(0x90|0x1) = ~"subnormal|snan"1348 ret i1 %class1349}1350 1351define i1 @not_issubnormal_or_zero_or_qnan_d(double %x) {1352; CHECK32-LABEL: not_issubnormal_or_zero_or_qnan_d:1353; CHECK32: # %bb.0:1354; CHECK32-NEXT: fclass.d $fa0, $fa01355; CHECK32-NEXT: movfr2gr.s $a0, $fa01356; CHECK32-NEXT: andi $a0, $a0, 2051357; CHECK32-NEXT: sltu $a0, $zero, $a01358; CHECK32-NEXT: ret1359;1360; CHECK64-LABEL: not_issubnormal_or_zero_or_qnan_d:1361; CHECK64: # %bb.0:1362; CHECK64-NEXT: fclass.d $fa0, $fa01363; CHECK64-NEXT: movfr2gr.d $a0, $fa01364; CHECK64-NEXT: andi $a0, $a0, 2051365; CHECK64-NEXT: sltu $a0, $zero, $a01366; CHECK64-NEXT: ret1367 %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 781) ; ~(0x90|0x2) = ~"subnormal|qnan"1368 ret i1 %class1369}1370 1371declare i1 @llvm.is.fpclass.f64(double, i32)1372