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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5define void @vabs_b(ptr %dst, ptr %src) {6; CHECK-LABEL: vabs_b:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: xvld $xr0, $a1, 09; CHECK-NEXT: xvsigncov.b $xr0, $xr0, $xr010; CHECK-NEXT: xvst $xr0, $a0, 011; CHECK-NEXT: ret12entry:13 %a = load <32 x i8>, ptr %src14 %b = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 true)15 store <32 x i8> %b, ptr %dst16 ret void17}18 19define void @vabs_b_1(ptr %dst, ptr %src) {20; CHECK-LABEL: vabs_b_1:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvld $xr0, $a1, 023; CHECK-NEXT: xvsigncov.b $xr0, $xr0, $xr024; CHECK-NEXT: xvst $xr0, $a0, 025; CHECK-NEXT: ret26entry:27 %a = load <32 x i8>, ptr %src28 %b = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false)29 store <32 x i8> %b, ptr %dst30 ret void31}32 33define void @vabs_h(ptr %dst, ptr %src) {34; CHECK-LABEL: vabs_h:35; CHECK: # %bb.0: # %entry36; CHECK-NEXT: xvld $xr0, $a1, 037; CHECK-NEXT: xvsigncov.h $xr0, $xr0, $xr038; CHECK-NEXT: xvst $xr0, $a0, 039; CHECK-NEXT: ret40entry:41 %a = load <16 x i16>, ptr %src42 %b = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 true)43 store <16 x i16> %b, ptr %dst44 ret void45}46 47define void @vabs_h_1(ptr %dst, ptr %src) {48; CHECK-LABEL: vabs_h_1:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: xvld $xr0, $a1, 051; CHECK-NEXT: xvsigncov.h $xr0, $xr0, $xr052; CHECK-NEXT: xvst $xr0, $a0, 053; CHECK-NEXT: ret54entry:55 %a = load <16 x i16>, ptr %src56 %b = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false)57 store <16 x i16> %b, ptr %dst58 ret void59}60 61define void @vabs_w(ptr %dst, ptr %src) {62; CHECK-LABEL: vabs_w:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: xvld $xr0, $a1, 065; CHECK-NEXT: xvsigncov.w $xr0, $xr0, $xr066; CHECK-NEXT: xvst $xr0, $a0, 067; CHECK-NEXT: ret68entry:69 %a = load <8 x i32>, ptr %src70 %b = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 true)71 store <8 x i32> %b, ptr %dst72 ret void73}74 75define void @vabs_w_1(ptr %dst, ptr %src) {76; CHECK-LABEL: vabs_w_1:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: xvld $xr0, $a1, 079; CHECK-NEXT: xvsigncov.w $xr0, $xr0, $xr080; CHECK-NEXT: xvst $xr0, $a0, 081; CHECK-NEXT: ret82entry:83 %a = load <8 x i32>, ptr %src84 %b = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false)85 store <8 x i32> %b, ptr %dst86 ret void87}88 89define void @vabs_d(ptr %dst, ptr %src) {90; CHECK-LABEL: vabs_d:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: xvld $xr0, $a1, 093; CHECK-NEXT: xvsigncov.d $xr0, $xr0, $xr094; CHECK-NEXT: xvst $xr0, $a0, 095; CHECK-NEXT: ret96entry:97 %a = load <4 x i64>, ptr %src98 %b = tail call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 true)99 store <4 x i64> %b, ptr %dst100 ret void101}102 103define void @vabs_d_1(ptr %dst, ptr %src) {104; CHECK-LABEL: vabs_d_1:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: xvld $xr0, $a1, 0107; CHECK-NEXT: xvsigncov.d $xr0, $xr0, $xr0108; CHECK-NEXT: xvst $xr0, $a0, 0109; CHECK-NEXT: ret110entry:111 %a = load <4 x i64>, ptr %src112 %b = tail call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false)113 store <4 x i64> %b, ptr %dst114 ret void115}116 117declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)118declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)119declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)120declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)121