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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8>)6 7define <16 x i16> @lasx_vext2xv_h_b(<32 x i8> %va) nounwind {8; CHECK-LABEL: lasx_vext2xv_h_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vext2xv.h.b $xr0, $xr011; CHECK-NEXT: ret12entry:13 %res = call <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8> %va)14 ret <16 x i16> %res15}16 17declare <8 x i32> @llvm.loongarch.lasx.vext2xv.w.b(<32 x i8>)18 19define <8 x i32> @lasx_vext2xv_w_b(<32 x i8> %va) nounwind {20; CHECK-LABEL: lasx_vext2xv_w_b:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vext2xv.w.b $xr0, $xr023; CHECK-NEXT: ret24entry:25 %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.w.b(<32 x i8> %va)26 ret <8 x i32> %res27}28 29declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.b(<32 x i8>)30 31define <4 x i64> @lasx_vext2xv_d_b(<32 x i8> %va) nounwind {32; CHECK-LABEL: lasx_vext2xv_d_b:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vext2xv.d.b $xr0, $xr035; CHECK-NEXT: ret36entry:37 %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.b(<32 x i8> %va)38 ret <4 x i64> %res39}40 41declare <8 x i32> @llvm.loongarch.lasx.vext2xv.w.h(<16 x i16>)42 43define <8 x i32> @lasx_vext2xv_w_h(<16 x i16> %va) nounwind {44; CHECK-LABEL: lasx_vext2xv_w_h:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vext2xv.w.h $xr0, $xr047; CHECK-NEXT: ret48entry:49 %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.w.h(<16 x i16> %va)50 ret <8 x i32> %res51}52 53declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.h(<16 x i16>)54 55define <4 x i64> @lasx_vext2xv_d_h(<16 x i16> %va) nounwind {56; CHECK-LABEL: lasx_vext2xv_d_h:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vext2xv.d.h $xr0, $xr059; CHECK-NEXT: ret60entry:61 %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.h(<16 x i16> %va)62 ret <4 x i64> %res63}64 65declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.w(<8 x i32>)66 67define <4 x i64> @lasx_vext2xv_d_w(<8 x i32> %va) nounwind {68; CHECK-LABEL: lasx_vext2xv_d_w:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vext2xv.d.w $xr0, $xr071; CHECK-NEXT: ret72entry:73 %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.w(<8 x i32> %va)74 ret <4 x i64> %res75}76 77declare <16 x i16> @llvm.loongarch.lasx.vext2xv.hu.bu(<32 x i8>)78 79define <16 x i16> @lasx_vext2xv_hu_bu(<32 x i8> %va) nounwind {80; CHECK-LABEL: lasx_vext2xv_hu_bu:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr083; CHECK-NEXT: ret84entry:85 %res = call <16 x i16> @llvm.loongarch.lasx.vext2xv.hu.bu(<32 x i8> %va)86 ret <16 x i16> %res87}88 89declare <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.bu(<32 x i8>)90 91define <8 x i32> @lasx_vext2xv_wu_bu(<32 x i8> %va) nounwind {92; CHECK-LABEL: lasx_vext2xv_wu_bu:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: vext2xv.wu.bu $xr0, $xr095; CHECK-NEXT: ret96entry:97 %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.bu(<32 x i8> %va)98 ret <8 x i32> %res99}100 101declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.bu(<32 x i8>)102 103define <4 x i64> @lasx_vext2xv_du_bu(<32 x i8> %va) nounwind {104; CHECK-LABEL: lasx_vext2xv_du_bu:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vext2xv.du.bu $xr0, $xr0107; CHECK-NEXT: ret108entry:109 %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.bu(<32 x i8> %va)110 ret <4 x i64> %res111}112 113declare <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.hu(<16 x i16>)114 115define <8 x i32> @lasx_vext2xv_wu_hu(<16 x i16> %va) nounwind {116; CHECK-LABEL: lasx_vext2xv_wu_hu:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0119; CHECK-NEXT: ret120entry:121 %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.hu(<16 x i16> %va)122 ret <8 x i32> %res123}124 125declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.hu(<16 x i16>)126 127define <4 x i64> @lasx_vext2xv_du_hu(<16 x i16> %va) nounwind {128; CHECK-LABEL: lasx_vext2xv_du_hu:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vext2xv.du.hu $xr0, $xr0131; CHECK-NEXT: ret132entry:133 %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.hu(<16 x i16> %va)134 ret <4 x i64> %res135}136 137declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.wu(<8 x i32>)138 139define <4 x i64> @lasx_vext2xv_du_wu(<8 x i32> %va) nounwind {140; CHECK-LABEL: lasx_vext2xv_du_wu:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0143; CHECK-NEXT: ret144entry:145 %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.wu(<8 x i32> %va)146 ret <4 x i64> %res147}148