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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8>)6 7define <16 x i16> @lasx_xvexth_h_b(<32 x i8> %va) nounwind {8; CHECK-LABEL: lasx_xvexth_h_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvexth.h.b $xr0, $xr011; CHECK-NEXT: ret12entry:13 %res = call <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8> %va)14 ret <16 x i16> %res15}16 17declare <8 x i32> @llvm.loongarch.lasx.xvexth.w.h(<16 x i16>)18 19define <8 x i32> @lasx_xvexth_w_h(<16 x i16> %va) nounwind {20; CHECK-LABEL: lasx_xvexth_w_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvexth.w.h $xr0, $xr023; CHECK-NEXT: ret24entry:25 %res = call <8 x i32> @llvm.loongarch.lasx.xvexth.w.h(<16 x i16> %va)26 ret <8 x i32> %res27}28 29declare <4 x i64> @llvm.loongarch.lasx.xvexth.d.w(<8 x i32>)30 31define <4 x i64> @lasx_xvexth_d_w(<8 x i32> %va) nounwind {32; CHECK-LABEL: lasx_xvexth_d_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: xvexth.d.w $xr0, $xr035; CHECK-NEXT: ret36entry:37 %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.d.w(<8 x i32> %va)38 ret <4 x i64> %res39}40 41declare <4 x i64> @llvm.loongarch.lasx.xvexth.q.d(<4 x i64>)42 43define <4 x i64> @lasx_xvexth_q_d(<4 x i64> %va) nounwind {44; CHECK-LABEL: lasx_xvexth_q_d:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: xvexth.q.d $xr0, $xr047; CHECK-NEXT: ret48entry:49 %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.q.d(<4 x i64> %va)50 ret <4 x i64> %res51}52 53declare <16 x i16> @llvm.loongarch.lasx.xvexth.hu.bu(<32 x i8>)54 55define <16 x i16> @lasx_xvexth_hu_bu(<32 x i8> %va) nounwind {56; CHECK-LABEL: lasx_xvexth_hu_bu:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: xvexth.hu.bu $xr0, $xr059; CHECK-NEXT: ret60entry:61 %res = call <16 x i16> @llvm.loongarch.lasx.xvexth.hu.bu(<32 x i8> %va)62 ret <16 x i16> %res63}64 65declare <8 x i32> @llvm.loongarch.lasx.xvexth.wu.hu(<16 x i16>)66 67define <8 x i32> @lasx_xvexth_wu_hu(<16 x i16> %va) nounwind {68; CHECK-LABEL: lasx_xvexth_wu_hu:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: xvexth.wu.hu $xr0, $xr071; CHECK-NEXT: ret72entry:73 %res = call <8 x i32> @llvm.loongarch.lasx.xvexth.wu.hu(<16 x i16> %va)74 ret <8 x i32> %res75}76 77declare <4 x i64> @llvm.loongarch.lasx.xvexth.du.wu(<8 x i32>)78 79define <4 x i64> @lasx_xvexth_du_wu(<8 x i32> %va) nounwind {80; CHECK-LABEL: lasx_xvexth_du_wu:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: xvexth.du.wu $xr0, $xr083; CHECK-NEXT: ret84entry:85 %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.du.wu(<8 x i32> %va)86 ret <4 x i64> %res87}88 89declare <4 x i64> @llvm.loongarch.lasx.xvexth.qu.du(<4 x i64>)90 91define <4 x i64> @lasx_xvexth_qu_du(<4 x i64> %va) nounwind {92; CHECK-LABEL: lasx_xvexth_qu_du:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: xvexth.qu.du $xr0, $xr095; CHECK-NEXT: ret96entry:97 %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.qu.du(<4 x i64> %va)98 ret <4 x i64> %res99}100