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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32)6 7define <8 x i32> @lasx_xvinsgr2vr_w(<8 x i32> %va) nounwind {8; CHECK-LABEL: lasx_xvinsgr2vr_w:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: ori $a0, $zero, 111; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 112; CHECK-NEXT: ret13entry:14 %res = call <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32> %va, i32 1, i32 1)15 ret <8 x i32> %res16}17 18declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32)19 20define <4 x i64> @lasx_xvinsgr2vr_d(<4 x i64> %va) nounwind {21; LA32-LABEL: lasx_xvinsgr2vr_d:22; LA32: # %bb.0: # %entry23; LA32-NEXT: ori $a0, $zero, 124; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 225; LA32-NEXT: xvinsgr2vr.w $xr0, $zero, 326; LA32-NEXT: ret27;28; LA64-LABEL: lasx_xvinsgr2vr_d:29; LA64: # %bb.0: # %entry30; LA64-NEXT: ori $a0, $zero, 131; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 132; LA64-NEXT: ret33entry:34 %res = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %va, i64 1, i32 1)35 ret <4 x i64> %res36}37