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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32)6 7define <8 x i32> @lasx_xvinsve0_w(<8 x i32> %va, <8 x i32> %vb) nounwind {8; CHECK-LABEL: lasx_xvinsve0_w:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvinsve0.w $xr0, $xr1, 111; CHECK-NEXT: ret12entry:13 %res = call <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32> %va, <8 x i32> %vb, i32 1)14 ret <8 x i32> %res15}16 17declare <4 x i64> @llvm.loongarch.lasx.xvinsve0.d(<4 x i64>, <4 x i64>, i32)18 19define <4 x i64> @lasx_xvinsve0_d(<4 x i64> %va, <4 x i64> %vb) nounwind {20; CHECK-LABEL: lasx_xvinsve0_d:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvinsve0.d $xr0, $xr1, 123; CHECK-NEXT: ret24entry:25 %res = call <4 x i64> @llvm.loongarch.lasx.xvinsve0.d(<4 x i64> %va, <4 x i64> %vb, i32 1)26 ret <4 x i64> %res27}28