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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.b(<32 x i8>, <32 x i8>)6 7define <16 x i16> @lasx_xvmulwev_h_b(<32 x i8> %va, <32 x i8> %vb) nounwind {8; CHECK-LABEL: lasx_xvmulwev_h_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvmulwev.h.b $xr0, $xr0, $xr111; CHECK-NEXT: ret12entry:13 %res = call <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.b(<32 x i8> %va, <32 x i8> %vb)14 ret <16 x i16> %res15}16 17declare <8 x i32> @llvm.loongarch.lasx.xvmulwev.w.h(<16 x i16>, <16 x i16>)18 19define <8 x i32> @lasx_xvmulwev_w_h(<16 x i16> %va, <16 x i16> %vb) nounwind {20; CHECK-LABEL: lasx_xvmulwev_w_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvmulwev.w.h $xr0, $xr0, $xr123; CHECK-NEXT: ret24entry:25 %res = call <8 x i32> @llvm.loongarch.lasx.xvmulwev.w.h(<16 x i16> %va, <16 x i16> %vb)26 ret <8 x i32> %res27}28 29declare <4 x i64> @llvm.loongarch.lasx.xvmulwev.d.w(<8 x i32>, <8 x i32>)30 31define <4 x i64> @lasx_xvmulwev_d_w(<8 x i32> %va, <8 x i32> %vb) nounwind {32; CHECK-LABEL: lasx_xvmulwev_d_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: xvmulwev.d.w $xr0, $xr0, $xr135; CHECK-NEXT: ret36entry:37 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwev.d.w(<8 x i32> %va, <8 x i32> %vb)38 ret <4 x i64> %res39}40 41declare <4 x i64> @llvm.loongarch.lasx.xvmulwev.q.d(<4 x i64>, <4 x i64>)42 43define <4 x i64> @lasx_xvmulwev_q_d(<4 x i64> %va, <4 x i64> %vb) nounwind {44; CHECK-LABEL: lasx_xvmulwev_q_d:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: xvmulwev.q.d $xr0, $xr0, $xr147; CHECK-NEXT: ret48entry:49 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwev.q.d(<4 x i64> %va, <4 x i64> %vb)50 ret <4 x i64> %res51}52 53declare <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.bu(<32 x i8>, <32 x i8>)54 55define <16 x i16> @lasx_xvmulwev_h_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {56; CHECK-LABEL: lasx_xvmulwev_h_bu:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: xvmulwev.h.bu $xr0, $xr0, $xr159; CHECK-NEXT: ret60entry:61 %res = call <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.bu(<32 x i8> %va, <32 x i8> %vb)62 ret <16 x i16> %res63}64 65declare <8 x i32> @llvm.loongarch.lasx.xvmulwev.w.hu(<16 x i16>, <16 x i16>)66 67define <8 x i32> @lasx_xvmulwev_w_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {68; CHECK-LABEL: lasx_xvmulwev_w_hu:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: xvmulwev.w.hu $xr0, $xr0, $xr171; CHECK-NEXT: ret72entry:73 %res = call <8 x i32> @llvm.loongarch.lasx.xvmulwev.w.hu(<16 x i16> %va, <16 x i16> %vb)74 ret <8 x i32> %res75}76 77declare <4 x i64> @llvm.loongarch.lasx.xvmulwev.d.wu(<8 x i32>, <8 x i32>)78 79define <4 x i64> @lasx_xvmulwev_d_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {80; CHECK-LABEL: lasx_xvmulwev_d_wu:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: xvmulwev.d.wu $xr0, $xr0, $xr183; CHECK-NEXT: ret84entry:85 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwev.d.wu(<8 x i32> %va, <8 x i32> %vb)86 ret <4 x i64> %res87}88 89declare <4 x i64> @llvm.loongarch.lasx.xvmulwev.q.du(<4 x i64>, <4 x i64>)90 91define <4 x i64> @lasx_xvmulwev_q_du(<4 x i64> %va, <4 x i64> %vb) nounwind {92; CHECK-LABEL: lasx_xvmulwev_q_du:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: xvmulwev.q.du $xr0, $xr0, $xr195; CHECK-NEXT: ret96entry:97 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwev.q.du(<4 x i64> %va, <4 x i64> %vb)98 ret <4 x i64> %res99}100 101declare <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.bu.b(<32 x i8>, <32 x i8>)102 103define <16 x i16> @lasx_xvmulwev_h_bu_b(<32 x i8> %va, <32 x i8> %vb) nounwind {104; CHECK-LABEL: lasx_xvmulwev_h_bu_b:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: xvmulwev.h.bu.b $xr0, $xr0, $xr1107; CHECK-NEXT: ret108entry:109 %res = call <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.bu.b(<32 x i8> %va, <32 x i8> %vb)110 ret <16 x i16> %res111}112 113declare <8 x i32> @llvm.loongarch.lasx.xvmulwev.w.hu.h(<16 x i16>, <16 x i16>)114 115define <8 x i32> @lasx_xvmulwev_w_hu_h(<16 x i16> %va, <16 x i16> %vb) nounwind {116; CHECK-LABEL: lasx_xvmulwev_w_hu_h:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: xvmulwev.w.hu.h $xr0, $xr0, $xr1119; CHECK-NEXT: ret120entry:121 %res = call <8 x i32> @llvm.loongarch.lasx.xvmulwev.w.hu.h(<16 x i16> %va, <16 x i16> %vb)122 ret <8 x i32> %res123}124 125declare <4 x i64> @llvm.loongarch.lasx.xvmulwev.d.wu.w(<8 x i32>, <8 x i32>)126 127define <4 x i64> @lasx_xvmulwev_d_wu_w(<8 x i32> %va, <8 x i32> %vb) nounwind {128; CHECK-LABEL: lasx_xvmulwev_d_wu_w:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: xvmulwev.d.wu.w $xr0, $xr0, $xr1131; CHECK-NEXT: ret132entry:133 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwev.d.wu.w(<8 x i32> %va, <8 x i32> %vb)134 ret <4 x i64> %res135}136 137declare <4 x i64> @llvm.loongarch.lasx.xvmulwev.q.du.d(<4 x i64>, <4 x i64>)138 139define <4 x i64> @lasx_xvmulwev_q_du_d(<4 x i64> %va, <4 x i64> %vb) nounwind {140; CHECK-LABEL: lasx_xvmulwev_q_du_d:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: xvmulwev.q.du.d $xr0, $xr0, $xr1143; CHECK-NEXT: ret144entry:145 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwev.q.du.d(<4 x i64> %va, <4 x i64> %vb)146 ret <4 x i64> %res147}148 149declare <16 x i16> @llvm.loongarch.lasx.xvmulwod.h.b(<32 x i8>, <32 x i8>)150 151define <16 x i16> @lasx_xvmulwod_h_b(<32 x i8> %va, <32 x i8> %vb) nounwind {152; CHECK-LABEL: lasx_xvmulwod_h_b:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: xvmulwod.h.b $xr0, $xr0, $xr1155; CHECK-NEXT: ret156entry:157 %res = call <16 x i16> @llvm.loongarch.lasx.xvmulwod.h.b(<32 x i8> %va, <32 x i8> %vb)158 ret <16 x i16> %res159}160 161declare <8 x i32> @llvm.loongarch.lasx.xvmulwod.w.h(<16 x i16>, <16 x i16>)162 163define <8 x i32> @lasx_xvmulwod_w_h(<16 x i16> %va, <16 x i16> %vb) nounwind {164; CHECK-LABEL: lasx_xvmulwod_w_h:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: xvmulwod.w.h $xr0, $xr0, $xr1167; CHECK-NEXT: ret168entry:169 %res = call <8 x i32> @llvm.loongarch.lasx.xvmulwod.w.h(<16 x i16> %va, <16 x i16> %vb)170 ret <8 x i32> %res171}172 173declare <4 x i64> @llvm.loongarch.lasx.xvmulwod.d.w(<8 x i32>, <8 x i32>)174 175define <4 x i64> @lasx_xvmulwod_d_w(<8 x i32> %va, <8 x i32> %vb) nounwind {176; CHECK-LABEL: lasx_xvmulwod_d_w:177; CHECK: # %bb.0: # %entry178; CHECK-NEXT: xvmulwod.d.w $xr0, $xr0, $xr1179; CHECK-NEXT: ret180entry:181 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwod.d.w(<8 x i32> %va, <8 x i32> %vb)182 ret <4 x i64> %res183}184 185declare <4 x i64> @llvm.loongarch.lasx.xvmulwod.q.d(<4 x i64>, <4 x i64>)186 187define <4 x i64> @lasx_xvmulwod_q_d(<4 x i64> %va, <4 x i64> %vb) nounwind {188; CHECK-LABEL: lasx_xvmulwod_q_d:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: xvmulwod.q.d $xr0, $xr0, $xr1191; CHECK-NEXT: ret192entry:193 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwod.q.d(<4 x i64> %va, <4 x i64> %vb)194 ret <4 x i64> %res195}196 197declare <16 x i16> @llvm.loongarch.lasx.xvmulwod.h.bu(<32 x i8>, <32 x i8>)198 199define <16 x i16> @lasx_xvmulwod_h_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {200; CHECK-LABEL: lasx_xvmulwod_h_bu:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: xvmulwod.h.bu $xr0, $xr0, $xr1203; CHECK-NEXT: ret204entry:205 %res = call <16 x i16> @llvm.loongarch.lasx.xvmulwod.h.bu(<32 x i8> %va, <32 x i8> %vb)206 ret <16 x i16> %res207}208 209declare <8 x i32> @llvm.loongarch.lasx.xvmulwod.w.hu(<16 x i16>, <16 x i16>)210 211define <8 x i32> @lasx_xvmulwod_w_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {212; CHECK-LABEL: lasx_xvmulwod_w_hu:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: xvmulwod.w.hu $xr0, $xr0, $xr1215; CHECK-NEXT: ret216entry:217 %res = call <8 x i32> @llvm.loongarch.lasx.xvmulwod.w.hu(<16 x i16> %va, <16 x i16> %vb)218 ret <8 x i32> %res219}220 221declare <4 x i64> @llvm.loongarch.lasx.xvmulwod.d.wu(<8 x i32>, <8 x i32>)222 223define <4 x i64> @lasx_xvmulwod_d_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {224; CHECK-LABEL: lasx_xvmulwod_d_wu:225; CHECK: # %bb.0: # %entry226; CHECK-NEXT: xvmulwod.d.wu $xr0, $xr0, $xr1227; CHECK-NEXT: ret228entry:229 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwod.d.wu(<8 x i32> %va, <8 x i32> %vb)230 ret <4 x i64> %res231}232 233declare <4 x i64> @llvm.loongarch.lasx.xvmulwod.q.du(<4 x i64>, <4 x i64>)234 235define <4 x i64> @lasx_xvmulwod_q_du(<4 x i64> %va, <4 x i64> %vb) nounwind {236; CHECK-LABEL: lasx_xvmulwod_q_du:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: xvmulwod.q.du $xr0, $xr0, $xr1239; CHECK-NEXT: ret240entry:241 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwod.q.du(<4 x i64> %va, <4 x i64> %vb)242 ret <4 x i64> %res243}244 245declare <16 x i16> @llvm.loongarch.lasx.xvmulwod.h.bu.b(<32 x i8>, <32 x i8>)246 247define <16 x i16> @lasx_xvmulwod_h_bu_b(<32 x i8> %va, <32 x i8> %vb) nounwind {248; CHECK-LABEL: lasx_xvmulwod_h_bu_b:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: xvmulwod.h.bu.b $xr0, $xr0, $xr1251; CHECK-NEXT: ret252entry:253 %res = call <16 x i16> @llvm.loongarch.lasx.xvmulwod.h.bu.b(<32 x i8> %va, <32 x i8> %vb)254 ret <16 x i16> %res255}256 257declare <8 x i32> @llvm.loongarch.lasx.xvmulwod.w.hu.h(<16 x i16>, <16 x i16>)258 259define <8 x i32> @lasx_xvmulwod_w_hu_h(<16 x i16> %va, <16 x i16> %vb) nounwind {260; CHECK-LABEL: lasx_xvmulwod_w_hu_h:261; CHECK: # %bb.0: # %entry262; CHECK-NEXT: xvmulwod.w.hu.h $xr0, $xr0, $xr1263; CHECK-NEXT: ret264entry:265 %res = call <8 x i32> @llvm.loongarch.lasx.xvmulwod.w.hu.h(<16 x i16> %va, <16 x i16> %vb)266 ret <8 x i32> %res267}268 269declare <4 x i64> @llvm.loongarch.lasx.xvmulwod.d.wu.w(<8 x i32>, <8 x i32>)270 271define <4 x i64> @lasx_xvmulwod_d_wu_w(<8 x i32> %va, <8 x i32> %vb) nounwind {272; CHECK-LABEL: lasx_xvmulwod_d_wu_w:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: xvmulwod.d.wu.w $xr0, $xr0, $xr1275; CHECK-NEXT: ret276entry:277 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwod.d.wu.w(<8 x i32> %va, <8 x i32> %vb)278 ret <4 x i64> %res279}280 281declare <4 x i64> @llvm.loongarch.lasx.xvmulwod.q.du.d(<4 x i64>, <4 x i64>)282 283define <4 x i64> @lasx_xvmulwod_q_du_d(<4 x i64> %va, <4 x i64> %vb) nounwind {284; CHECK-LABEL: lasx_xvmulwod_q_du_d:285; CHECK: # %bb.0: # %entry286; CHECK-NEXT: xvmulwod.q.du.d $xr0, $xr0, $xr1287; CHECK-NEXT: ret288entry:289 %res = call <4 x i64> @llvm.loongarch.lasx.xvmulwod.q.du.d(<4 x i64> %va, <4 x i64> %vb)290 ret <4 x i64> %res291}292