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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <32 x i8> @llvm.loongarch.lasx.xvreplve0.b(<32 x i8>)6 7define <32 x i8> @lasx_xvreplve0_b(<32 x i8> %va) nounwind {8; CHECK-LABEL: lasx_xvreplve0_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvreplve0.b $xr0, $xr011; CHECK-NEXT: ret12entry:13 %res = call <32 x i8> @llvm.loongarch.lasx.xvreplve0.b(<32 x i8> %va)14 ret <32 x i8> %res15}16 17declare <16 x i16> @llvm.loongarch.lasx.xvreplve0.h(<16 x i16>)18 19define <16 x i16> @lasx_xvreplve0_h(<16 x i16> %va) nounwind {20; CHECK-LABEL: lasx_xvreplve0_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvreplve0.h $xr0, $xr023; CHECK-NEXT: ret24entry:25 %res = call <16 x i16> @llvm.loongarch.lasx.xvreplve0.h(<16 x i16> %va)26 ret <16 x i16> %res27}28 29declare <8 x i32> @llvm.loongarch.lasx.xvreplve0.w(<8 x i32>)30 31define <8 x i32> @lasx_xvreplve0_w(<8 x i32> %va) nounwind {32; CHECK-LABEL: lasx_xvreplve0_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: xvreplve0.w $xr0, $xr035; CHECK-NEXT: ret36entry:37 %res = call <8 x i32> @llvm.loongarch.lasx.xvreplve0.w(<8 x i32> %va)38 ret <8 x i32> %res39}40 41declare <4 x i64> @llvm.loongarch.lasx.xvreplve0.d(<4 x i64>)42 43define <4 x i64> @lasx_xvreplve0_d(<4 x i64> %va) nounwind {44; CHECK-LABEL: lasx_xvreplve0_d:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: xvreplve0.d $xr0, $xr047; CHECK-NEXT: ret48entry:49 %res = call <4 x i64> @llvm.loongarch.lasx.xvreplve0.d(<4 x i64> %va)50 ret <4 x i64> %res51}52 53declare <32 x i8> @llvm.loongarch.lasx.xvreplve0.q(<32 x i8>)54 55define <32 x i8> @lasx_xvreplve0_q(<32 x i8> %va) nounwind {56; CHECK-LABEL: lasx_xvreplve0_q:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: xvreplve0.q $xr0, $xr059; CHECK-NEXT: ret60entry:61 %res = call <32 x i8> @llvm.loongarch.lasx.xvreplve0.q(<32 x i8> %va)62 ret <32 x i8> %res63}64