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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <32 x i8> @llvm.loongarch.lasx.xvsadd.b(<32 x i8>, <32 x i8>)6 7define <32 x i8> @lasx_xvsadd_b(<32 x i8> %va, <32 x i8> %vb) nounwind {8; CHECK-LABEL: lasx_xvsadd_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvsadd.b $xr0, $xr0, $xr111; CHECK-NEXT: ret12entry:13 %res = call <32 x i8> @llvm.loongarch.lasx.xvsadd.b(<32 x i8> %va, <32 x i8> %vb)14 ret <32 x i8> %res15}16 17declare <16 x i16> @llvm.loongarch.lasx.xvsadd.h(<16 x i16>, <16 x i16>)18 19define <16 x i16> @lasx_xvsadd_h(<16 x i16> %va, <16 x i16> %vb) nounwind {20; CHECK-LABEL: lasx_xvsadd_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvsadd.h $xr0, $xr0, $xr123; CHECK-NEXT: ret24entry:25 %res = call <16 x i16> @llvm.loongarch.lasx.xvsadd.h(<16 x i16> %va, <16 x i16> %vb)26 ret <16 x i16> %res27}28 29declare <8 x i32> @llvm.loongarch.lasx.xvsadd.w(<8 x i32>, <8 x i32>)30 31define <8 x i32> @lasx_xvsadd_w(<8 x i32> %va, <8 x i32> %vb) nounwind {32; CHECK-LABEL: lasx_xvsadd_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: xvsadd.w $xr0, $xr0, $xr135; CHECK-NEXT: ret36entry:37 %res = call <8 x i32> @llvm.loongarch.lasx.xvsadd.w(<8 x i32> %va, <8 x i32> %vb)38 ret <8 x i32> %res39}40 41declare <4 x i64> @llvm.loongarch.lasx.xvsadd.d(<4 x i64>, <4 x i64>)42 43define <4 x i64> @lasx_xvsadd_d(<4 x i64> %va, <4 x i64> %vb) nounwind {44; CHECK-LABEL: lasx_xvsadd_d:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: xvsadd.d $xr0, $xr0, $xr147; CHECK-NEXT: ret48entry:49 %res = call <4 x i64> @llvm.loongarch.lasx.xvsadd.d(<4 x i64> %va, <4 x i64> %vb)50 ret <4 x i64> %res51}52 53declare <32 x i8> @llvm.loongarch.lasx.xvsadd.bu(<32 x i8>, <32 x i8>)54 55define <32 x i8> @lasx_xvsadd_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {56; CHECK-LABEL: lasx_xvsadd_bu:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: xvsadd.bu $xr0, $xr0, $xr159; CHECK-NEXT: ret60entry:61 %res = call <32 x i8> @llvm.loongarch.lasx.xvsadd.bu(<32 x i8> %va, <32 x i8> %vb)62 ret <32 x i8> %res63}64 65declare <16 x i16> @llvm.loongarch.lasx.xvsadd.hu(<16 x i16>, <16 x i16>)66 67define <16 x i16> @lasx_xvsadd_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {68; CHECK-LABEL: lasx_xvsadd_hu:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: xvsadd.hu $xr0, $xr0, $xr171; CHECK-NEXT: ret72entry:73 %res = call <16 x i16> @llvm.loongarch.lasx.xvsadd.hu(<16 x i16> %va, <16 x i16> %vb)74 ret <16 x i16> %res75}76 77declare <8 x i32> @llvm.loongarch.lasx.xvsadd.wu(<8 x i32>, <8 x i32>)78 79define <8 x i32> @lasx_xvsadd_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {80; CHECK-LABEL: lasx_xvsadd_wu:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: xvsadd.wu $xr0, $xr0, $xr183; CHECK-NEXT: ret84entry:85 %res = call <8 x i32> @llvm.loongarch.lasx.xvsadd.wu(<8 x i32> %va, <8 x i32> %vb)86 ret <8 x i32> %res87}88 89declare <4 x i64> @llvm.loongarch.lasx.xvsadd.du(<4 x i64>, <4 x i64>)90 91define <4 x i64> @lasx_xvsadd_du(<4 x i64> %va, <4 x i64> %vb) nounwind {92; CHECK-LABEL: lasx_xvsadd_du:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: xvsadd.du $xr0, $xr0, $xr195; CHECK-NEXT: ret96entry:97 %res = call <4 x i64> @llvm.loongarch.lasx.xvsadd.du(<4 x i64> %va, <4 x i64> %vb)98 ret <4 x i64> %res99}100