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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32)6 7define <16 x i16> @lasx_xvsllwil_h_b(<32 x i8> %va) nounwind {8; CHECK-LABEL: lasx_xvsllwil_h_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvsllwil.h.b $xr0, $xr0, 111; CHECK-NEXT: ret12entry:13 %res = call <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8> %va, i32 1)14 ret <16 x i16> %res15}16 17declare <8 x i32> @llvm.loongarch.lasx.xvsllwil.w.h(<16 x i16>, i32)18 19define <8 x i32> @lasx_xvsllwil_w_h(<16 x i16> %va) nounwind {20; CHECK-LABEL: lasx_xvsllwil_w_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvsllwil.w.h $xr0, $xr0, 123; CHECK-NEXT: ret24entry:25 %res = call <8 x i32> @llvm.loongarch.lasx.xvsllwil.w.h(<16 x i16> %va, i32 1)26 ret <8 x i32> %res27}28 29declare <4 x i64> @llvm.loongarch.lasx.xvsllwil.d.w(<8 x i32>, i32)30 31define <4 x i64> @lasx_xvsllwil_d_w(<8 x i32> %va) nounwind {32; CHECK-LABEL: lasx_xvsllwil_d_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: xvsllwil.d.w $xr0, $xr0, 135; CHECK-NEXT: ret36entry:37 %res = call <4 x i64> @llvm.loongarch.lasx.xvsllwil.d.w(<8 x i32> %va, i32 1)38 ret <4 x i64> %res39}40 41declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.hu.bu(<32 x i8>, i32)42 43define <16 x i16> @lasx_xvsllwil_hu_bu(<32 x i8> %va) nounwind {44; CHECK-LABEL: lasx_xvsllwil_hu_bu:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: xvsllwil.hu.bu $xr0, $xr0, 147; CHECK-NEXT: ret48entry:49 %res = call <16 x i16> @llvm.loongarch.lasx.xvsllwil.hu.bu(<32 x i8> %va, i32 1)50 ret <16 x i16> %res51}52 53declare <8 x i32> @llvm.loongarch.lasx.xvsllwil.wu.hu(<16 x i16>, i32)54 55define <8 x i32> @lasx_xvsllwil_wu_hu(<16 x i16> %va) nounwind {56; CHECK-LABEL: lasx_xvsllwil_wu_hu:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: xvsllwil.wu.hu $xr0, $xr0, 159; CHECK-NEXT: ret60entry:61 %res = call <8 x i32> @llvm.loongarch.lasx.xvsllwil.wu.hu(<16 x i16> %va, i32 1)62 ret <8 x i32> %res63}64 65declare <4 x i64> @llvm.loongarch.lasx.xvsllwil.du.wu(<8 x i32>, i32)66 67define <4 x i64> @lasx_xvsllwil_du_wu(<8 x i32> %va) nounwind {68; CHECK-LABEL: lasx_xvsllwil_du_wu:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: xvsllwil.du.wu $xr0, $xr0, 171; CHECK-NEXT: ret72entry:73 %res = call <4 x i64> @llvm.loongarch.lasx.xvsllwil.du.wu(<8 x i32> %va, i32 1)74 ret <4 x i64> %res75}76