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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5declare <32 x i8> @llvm.loongarch.lasx.xvsrln.b.h(<16 x i16>, <16 x i16>)6 7define <32 x i8> @lasx_xvsrln_b_h(<16 x i16> %va, <16 x i16> %vb) nounwind {8; CHECK-LABEL: lasx_xvsrln_b_h:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xvsrln.b.h $xr0, $xr0, $xr111; CHECK-NEXT: ret12entry:13 %res = call <32 x i8> @llvm.loongarch.lasx.xvsrln.b.h(<16 x i16> %va, <16 x i16> %vb)14 ret <32 x i8> %res15}16 17declare <16 x i16> @llvm.loongarch.lasx.xvsrln.h.w(<8 x i32>, <8 x i32>)18 19define <16 x i16> @lasx_xvsrln_h_w(<8 x i32> %va, <8 x i32> %vb) nounwind {20; CHECK-LABEL: lasx_xvsrln_h_w:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: xvsrln.h.w $xr0, $xr0, $xr123; CHECK-NEXT: ret24entry:25 %res = call <16 x i16> @llvm.loongarch.lasx.xvsrln.h.w(<8 x i32> %va, <8 x i32> %vb)26 ret <16 x i16> %res27}28 29declare <8 x i32> @llvm.loongarch.lasx.xvsrln.w.d(<4 x i64>, <4 x i64>)30 31define <8 x i32> @lasx_xvsrln_w_d(<4 x i64> %va, <4 x i64> %vb) nounwind {32; CHECK-LABEL: lasx_xvsrln_w_d:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: xvsrln.w.d $xr0, $xr0, $xr135; CHECK-NEXT: ret36entry:37 %res = call <8 x i32> @llvm.loongarch.lasx.xvsrln.w.d(<4 x i64> %va, <4 x i64> %vb)38 ret <8 x i32> %res39}40