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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc -mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s4 5;; 1. trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b) or abdu(a,b)6;; 2. abs(sub_nsw(x, y)) -> abds(a,b)7;; 3. sub(smax(a,b),smin(a,b)) -> abds(a,b) or abdu(a,b)8;; 4. select(icmp(a,b, slt|ult),sub(a,b),sub(b,a)) -> abds(a,b) or abdu(a,b)9;; 5. sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abds(a,b) or abdu(a,b)10;;11;; abds / abdu can be lowered to xvabsd.{b/h/w/d} / xvabsd.{b/h/w/d}u instruction.12 13;; trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b)14define <32 x i8> @xvabsd_b(<32 x i8> %a, <32 x i8> %b) {15; CHECK-LABEL: xvabsd_b:16; CHECK: # %bb.0:17; CHECK-NEXT: xvabsd.b $xr0, $xr0, $xr118; CHECK-NEXT: ret19 %a.sext = sext <32 x i8> %a to <32 x i16>20 %b.sext = sext <32 x i8> %b to <32 x i16>21 %sub = sub <32 x i16> %a.sext, %b.sext22 %abs = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %sub, i1 true)23 %trunc = trunc <32 x i16> %abs to <32 x i8>24 ret <32 x i8> %trunc25}26 27define <16 x i16> @xvabsd_h(<16 x i16> %a, <16 x i16> %b) {28; CHECK-LABEL: xvabsd_h:29; CHECK: # %bb.0:30; CHECK-NEXT: xvabsd.h $xr0, $xr0, $xr131; CHECK-NEXT: ret32 %a.sext = sext <16 x i16> %a to <16 x i32>33 %b.sext = sext <16 x i16> %b to <16 x i32>34 %sub = sub <16 x i32> %a.sext, %b.sext35 %abs = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %sub, i1 true)36 %trunc = trunc <16 x i32> %abs to <16 x i16>37 ret <16 x i16> %trunc38}39 40define <8 x i32> @xvabsd_w(<8 x i32> %a, <8 x i32> %b) {41; CHECK-LABEL: xvabsd_w:42; CHECK: # %bb.0:43; CHECK-NEXT: xvabsd.w $xr0, $xr0, $xr144; CHECK-NEXT: ret45 %a.sext = sext <8 x i32> %a to <8 x i64>46 %b.sext = sext <8 x i32> %b to <8 x i64>47 %sub = sub <8 x i64> %a.sext, %b.sext48 %abs = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %sub, i1 true)49 %trunc = trunc <8 x i64> %abs to <8 x i32>50 ret <8 x i32> %trunc51}52 53define <4 x i64> @xvabsd_d(<4 x i64> %a, <4 x i64> %b) {54; CHECK-LABEL: xvabsd_d:55; CHECK: # %bb.0:56; CHECK-NEXT: xvabsd.d $xr0, $xr0, $xr157; CHECK-NEXT: ret58 %a.sext = sext <4 x i64> %a to <4 x i128>59 %b.sext = sext <4 x i64> %b to <4 x i128>60 %sub = sub <4 x i128> %a.sext, %b.sext61 %abs = call <4 x i128> @llvm.abs.v4i128(<4 x i128> %sub, i1 true)62 %trunc = trunc <4 x i128> %abs to <4 x i64>63 ret <4 x i64> %trunc64}65 66define <32 x i8> @xvabsd_bu(<32 x i8> %a, <32 x i8> %b) {67; CHECK-LABEL: xvabsd_bu:68; CHECK: # %bb.0:69; CHECK-NEXT: xvabsd.bu $xr0, $xr0, $xr170; CHECK-NEXT: ret71 %a.zext = zext <32 x i8> %a to <32 x i16>72 %b.zext = zext <32 x i8> %b to <32 x i16>73 %sub = sub <32 x i16> %a.zext, %b.zext74 %abs = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %sub, i1 true)75 %trunc = trunc <32 x i16> %abs to <32 x i8>76 ret <32 x i8> %trunc77}78 79define <16 x i16> @xvabsd_hu(<16 x i16> %a, <16 x i16> %b) {80; CHECK-LABEL: xvabsd_hu:81; CHECK: # %bb.0:82; CHECK-NEXT: xvabsd.hu $xr0, $xr0, $xr183; CHECK-NEXT: ret84 %a.zext = zext <16 x i16> %a to <16 x i32>85 %b.zext = zext <16 x i16> %b to <16 x i32>86 %sub = sub <16 x i32> %a.zext, %b.zext87 %abs = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %sub, i1 true)88 %trunc = trunc <16 x i32> %abs to <16 x i16>89 ret <16 x i16> %trunc90}91 92define <8 x i32> @xvabsd_wu(<8 x i32> %a, <8 x i32> %b) {93; CHECK-LABEL: xvabsd_wu:94; CHECK: # %bb.0:95; CHECK-NEXT: xvabsd.wu $xr0, $xr0, $xr196; CHECK-NEXT: ret97 %a.zext = zext <8 x i32> %a to <8 x i64>98 %b.zext = zext <8 x i32> %b to <8 x i64>99 %sub = sub <8 x i64> %a.zext, %b.zext100 %abs = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %sub, i1 true)101 %trunc = trunc <8 x i64> %abs to <8 x i32>102 ret <8 x i32> %trunc103}104 105define <4 x i64> @xvabsd_du(<4 x i64> %a, <4 x i64> %b) {106; CHECK-LABEL: xvabsd_du:107; CHECK: # %bb.0:108; CHECK-NEXT: xvabsd.du $xr0, $xr0, $xr1109; CHECK-NEXT: ret110 %a.zext = zext <4 x i64> %a to <4 x i128>111 %b.zext = zext <4 x i64> %b to <4 x i128>112 %sub = sub <4 x i128> %a.zext, %b.zext113 %abs = call <4 x i128> @llvm.abs.v4i128(<4 x i128> %sub, i1 true)114 %trunc = trunc <4 x i128> %abs to <4 x i64>115 ret <4 x i64> %trunc116}117 118;; abs(sub_nsw(x, y)) -> abds(a,b)119define <32 x i8> @xvabsd_b_nsw(<32 x i8> %a, <32 x i8> %b) {120; CHECK-LABEL: xvabsd_b_nsw:121; CHECK: # %bb.0:122; CHECK-NEXT: xvabsd.b $xr0, $xr0, $xr1123; CHECK-NEXT: ret124 %sub = sub nsw <32 x i8> %a, %b125 %abs = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %sub, i1 true)126 ret <32 x i8> %abs127}128 129define <16 x i16> @xvabsd_h_nsw(<16 x i16> %a, <16 x i16> %b) {130; CHECK-LABEL: xvabsd_h_nsw:131; CHECK: # %bb.0:132; CHECK-NEXT: xvabsd.h $xr0, $xr0, $xr1133; CHECK-NEXT: ret134 %sub = sub nsw <16 x i16> %a, %b135 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)136 ret <16 x i16> %abs137}138 139define <8 x i32> @xvabsd_w_nsw(<8 x i32> %a, <8 x i32> %b) {140; CHECK-LABEL: xvabsd_w_nsw:141; CHECK: # %bb.0:142; CHECK-NEXT: xvabsd.w $xr0, $xr0, $xr1143; CHECK-NEXT: ret144 %sub = sub nsw <8 x i32> %a, %b145 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)146 ret <8 x i32> %abs147}148 149define <4 x i64> @xvabsd_d_nsw(<4 x i64> %a, <4 x i64> %b) {150; CHECK-LABEL: xvabsd_d_nsw:151; CHECK: # %bb.0:152; CHECK-NEXT: xvabsd.d $xr0, $xr0, $xr1153; CHECK-NEXT: ret154 %sub = sub nsw <4 x i64> %a, %b155 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)156 ret <4 x i64> %abs157}158 159;; sub(smax(a,b),smin(a,b)) -> abds(a,b)160define <32 x i8> @maxmin_b(<32 x i8> %0, <32 x i8> %1) {161; CHECK-LABEL: maxmin_b:162; CHECK: # %bb.0:163; CHECK-NEXT: xvabsd.b $xr0, $xr0, $xr1164; CHECK-NEXT: ret165 %a = tail call <32 x i8> @llvm.smax.v32i8(<32 x i8> %0, <32 x i8> %1)166 %b = tail call <32 x i8> @llvm.smin.v32i8(<32 x i8> %0, <32 x i8> %1)167 %sub = sub <32 x i8> %a, %b168 ret <32 x i8> %sub169}170 171define <16 x i16> @maxmin_h(<16 x i16> %0, <16 x i16> %1) {172; CHECK-LABEL: maxmin_h:173; CHECK: # %bb.0:174; CHECK-NEXT: xvabsd.h $xr0, $xr0, $xr1175; CHECK-NEXT: ret176 %a = tail call <16 x i16> @llvm.smax.v16i16(<16 x i16> %0, <16 x i16> %1)177 %b = tail call <16 x i16> @llvm.smin.v16i16(<16 x i16> %0, <16 x i16> %1)178 %sub = sub <16 x i16> %a, %b179 ret <16 x i16> %sub180}181 182define <8 x i32> @maxmin_w(<8 x i32> %0, <8 x i32> %1) {183; CHECK-LABEL: maxmin_w:184; CHECK: # %bb.0:185; CHECK-NEXT: xvabsd.w $xr0, $xr0, $xr1186; CHECK-NEXT: ret187 %a = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> %0, <8 x i32> %1)188 %b = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> %0, <8 x i32> %1)189 %sub = sub <8 x i32> %a, %b190 ret <8 x i32> %sub191}192 193define <4 x i64> @maxmin_d(<4 x i64> %0, <4 x i64> %1) {194; CHECK-LABEL: maxmin_d:195; CHECK: # %bb.0:196; CHECK-NEXT: xvabsd.d $xr0, $xr0, $xr1197; CHECK-NEXT: ret198 %a = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> %0, <4 x i64> %1)199 %b = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> %0, <4 x i64> %1)200 %sub = sub <4 x i64> %a, %b201 ret <4 x i64> %sub202}203 204define <32 x i8> @maxmin_bu(<32 x i8> %0, <32 x i8> %1) {205; CHECK-LABEL: maxmin_bu:206; CHECK: # %bb.0:207; CHECK-NEXT: xvabsd.bu $xr0, $xr0, $xr1208; CHECK-NEXT: ret209 %a = tail call <32 x i8> @llvm.umax.v32i8(<32 x i8> %0, <32 x i8> %1)210 %b = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> %0, <32 x i8> %1)211 %sub = sub <32 x i8> %a, %b212 ret <32 x i8> %sub213}214 215define <16 x i16> @maxmin_hu(<16 x i16> %0, <16 x i16> %1) {216; CHECK-LABEL: maxmin_hu:217; CHECK: # %bb.0:218; CHECK-NEXT: xvabsd.hu $xr0, $xr0, $xr1219; CHECK-NEXT: ret220 %a = tail call <16 x i16> @llvm.umax.v16i16(<16 x i16> %0, <16 x i16> %1)221 %b = tail call <16 x i16> @llvm.umin.v16i16(<16 x i16> %0, <16 x i16> %1)222 %sub = sub <16 x i16> %a, %b223 ret <16 x i16> %sub224}225 226define <8 x i32> @maxmin_wu(<8 x i32> %0, <8 x i32> %1) {227; CHECK-LABEL: maxmin_wu:228; CHECK: # %bb.0:229; CHECK-NEXT: xvabsd.wu $xr0, $xr0, $xr1230; CHECK-NEXT: ret231 %a = tail call <8 x i32> @llvm.umax.v8i32(<8 x i32> %0, <8 x i32> %1)232 %b = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> %0, <8 x i32> %1)233 %sub = sub <8 x i32> %a, %b234 ret <8 x i32> %sub235}236 237define <4 x i64> @maxmin_du(<4 x i64> %0, <4 x i64> %1) {238; CHECK-LABEL: maxmin_du:239; CHECK: # %bb.0:240; CHECK-NEXT: xvabsd.du $xr0, $xr0, $xr1241; CHECK-NEXT: ret242 %a = tail call <4 x i64> @llvm.umax.v4i64(<4 x i64> %0, <4 x i64> %1)243 %b = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> %0, <4 x i64> %1)244 %sub = sub <4 x i64> %a, %b245 ret <4 x i64> %sub246}247 248define <32 x i8> @maxmin_bu_com1(<32 x i8> %0, <32 x i8> %1) {249; CHECK-LABEL: maxmin_bu_com1:250; CHECK: # %bb.0:251; CHECK-NEXT: xvabsd.bu $xr0, $xr0, $xr1252; CHECK-NEXT: ret253 %a = tail call <32 x i8> @llvm.umax.v32i8(<32 x i8> %0, <32 x i8> %1)254 %b = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> %1, <32 x i8> %0)255 %sub = sub <32 x i8> %a, %b256 ret <32 x i8> %sub257}258 259;; select(icmp(a,b, slt),sub(a,b),sub(b,a)) -> abds(a,b)260define <32 x i8> @xvabsd_b_cmp(<32 x i8> %a, <32 x i8> %b) nounwind {261; CHECK-LABEL: xvabsd_b_cmp:262; CHECK: # %bb.0:263; CHECK-NEXT: xvabsd.b $xr0, $xr0, $xr1264; CHECK-NEXT: ret265 %cmp = icmp slt <32 x i8> %a, %b266 %ab = sub <32 x i8> %a, %b267 %ba = sub <32 x i8> %b, %a268 %sel = select <32 x i1> %cmp, <32 x i8> %ba, <32 x i8> %ab269 ret <32 x i8> %sel270}271 272define <16 x i16> @xvabsd_h_cmp(<16 x i16> %a, <16 x i16> %b) nounwind {273; CHECK-LABEL: xvabsd_h_cmp:274; CHECK: # %bb.0:275; CHECK-NEXT: xvabsd.h $xr0, $xr0, $xr1276; CHECK-NEXT: ret277 %cmp = icmp slt <16 x i16> %a, %b278 %ab = sub <16 x i16> %a, %b279 %ba = sub <16 x i16> %b, %a280 %sel = select <16 x i1> %cmp, <16 x i16> %ba, <16 x i16> %ab281 ret <16 x i16> %sel282}283 284define <8 x i32> @xvabsd_w_cmp(<8 x i32> %a, <8 x i32> %b) nounwind {285; CHECK-LABEL: xvabsd_w_cmp:286; CHECK: # %bb.0:287; CHECK-NEXT: xvabsd.w $xr0, $xr0, $xr1288; CHECK-NEXT: ret289 %cmp = icmp slt <8 x i32> %a, %b290 %ab = sub <8 x i32> %a, %b291 %ba = sub <8 x i32> %b, %a292 %sel = select <8 x i1> %cmp, <8 x i32> %ba, <8 x i32> %ab293 ret <8 x i32> %sel294}295 296define <4 x i64> @xvabsd_d_cmp(<4 x i64> %a, <4 x i64> %b) nounwind {297; CHECK-LABEL: xvabsd_d_cmp:298; CHECK: # %bb.0:299; CHECK-NEXT: xvabsd.d $xr0, $xr0, $xr1300; CHECK-NEXT: ret301 %cmp = icmp slt <4 x i64> %a, %b302 %ab = sub <4 x i64> %a, %b303 %ba = sub <4 x i64> %b, %a304 %sel = select <4 x i1> %cmp, <4 x i64> %ba, <4 x i64> %ab305 ret <4 x i64> %sel306}307 308define <32 x i8> @xvabsd_bu_cmp(<32 x i8> %a, <32 x i8> %b) nounwind {309; CHECK-LABEL: xvabsd_bu_cmp:310; CHECK: # %bb.0:311; CHECK-NEXT: xvabsd.bu $xr0, $xr0, $xr1312; CHECK-NEXT: ret313 %cmp = icmp ult <32 x i8> %a, %b314 %ab = sub <32 x i8> %a, %b315 %ba = sub <32 x i8> %b, %a316 %sel = select <32 x i1> %cmp, <32 x i8> %ba, <32 x i8> %ab317 ret <32 x i8> %sel318}319 320define <16 x i16> @xvabsd_hu_cmp(<16 x i16> %a, <16 x i16> %b) nounwind {321; CHECK-LABEL: xvabsd_hu_cmp:322; CHECK: # %bb.0:323; CHECK-NEXT: xvabsd.hu $xr0, $xr0, $xr1324; CHECK-NEXT: ret325 %cmp = icmp ult <16 x i16> %a, %b326 %ab = sub <16 x i16> %a, %b327 %ba = sub <16 x i16> %b, %a328 %sel = select <16 x i1> %cmp, <16 x i16> %ba, <16 x i16> %ab329 ret <16 x i16> %sel330}331 332define <8 x i32> @xvabsd_wu_cmp(<8 x i32> %a, <8 x i32> %b) nounwind {333; CHECK-LABEL: xvabsd_wu_cmp:334; CHECK: # %bb.0:335; CHECK-NEXT: xvabsd.wu $xr0, $xr0, $xr1336; CHECK-NEXT: ret337 %cmp = icmp ult <8 x i32> %a, %b338 %ab = sub <8 x i32> %a, %b339 %ba = sub <8 x i32> %b, %a340 %sel = select <8 x i1> %cmp, <8 x i32> %ba, <8 x i32> %ab341 ret <8 x i32> %sel342}343 344define <4 x i64> @xvabsd_du_cmp(<4 x i64> %a, <4 x i64> %b) nounwind {345; CHECK-LABEL: xvabsd_du_cmp:346; CHECK: # %bb.0:347; CHECK-NEXT: xvabsd.du $xr0, $xr0, $xr1348; CHECK-NEXT: ret349 %cmp = icmp ult <4 x i64> %a, %b350 %ab = sub <4 x i64> %a, %b351 %ba = sub <4 x i64> %b, %a352 %sel = select <4 x i1> %cmp, <4 x i64> %ba, <4 x i64> %ab353 ret <4 x i64> %sel354}355 356;; sub(select(icmp(a,b, slt),a,b),select(icmp(a,b, slt),b,a)) -> abds(a,b)357define <32 x i8> @xvabsd_b_select(<32 x i8> %a, <32 x i8> %b) nounwind {358; CHECK-LABEL: xvabsd_b_select:359; CHECK: # %bb.0:360; CHECK-NEXT: xvabsd.b $xr0, $xr0, $xr1361; CHECK-NEXT: ret362 %cmp = icmp slt <32 x i8> %a, %b363 %ab = select <32 x i1> %cmp, <32 x i8> %a, <32 x i8> %b364 %ba = select <32 x i1> %cmp, <32 x i8> %b, <32 x i8> %a365 %sub = sub <32 x i8> %ba, %ab366 ret <32 x i8> %sub367}368 369define <16 x i16> @xvabsd_h_select(<16 x i16> %a, <16 x i16> %b) nounwind {370; CHECK-LABEL: xvabsd_h_select:371; CHECK: # %bb.0:372; CHECK-NEXT: xvabsd.h $xr0, $xr0, $xr1373; CHECK-NEXT: ret374 %cmp = icmp sle <16 x i16> %a, %b375 %ab = select <16 x i1> %cmp, <16 x i16> %a, <16 x i16> %b376 %ba = select <16 x i1> %cmp, <16 x i16> %b, <16 x i16> %a377 %sub = sub <16 x i16> %ba, %ab378 ret <16 x i16> %sub379}380 381define <8 x i32> @xvabsd_w_select(<8 x i32> %a, <8 x i32> %b) nounwind {382; CHECK-LABEL: xvabsd_w_select:383; CHECK: # %bb.0:384; CHECK-NEXT: xvabsd.w $xr0, $xr0, $xr1385; CHECK-NEXT: ret386 %cmp = icmp sgt <8 x i32> %a, %b387 %ab = select <8 x i1> %cmp, <8 x i32> %a, <8 x i32> %b388 %ba = select <8 x i1> %cmp, <8 x i32> %b, <8 x i32> %a389 %sub = sub <8 x i32> %ab, %ba390 ret <8 x i32> %sub391}392 393define <4 x i64> @xvabsd_d_select(<4 x i64> %a, <4 x i64> %b) nounwind {394; CHECK-LABEL: xvabsd_d_select:395; CHECK: # %bb.0:396; CHECK-NEXT: xvabsd.d $xr0, $xr0, $xr1397; CHECK-NEXT: ret398 %cmp = icmp sge <4 x i64> %a, %b399 %ab = select <4 x i1> %cmp, <4 x i64> %a, <4 x i64> %b400 %ba = select <4 x i1> %cmp, <4 x i64> %b, <4 x i64> %a401 %sub = sub <4 x i64> %ab, %ba402 ret <4 x i64> %sub403}404 405define <32 x i8> @xvabsd_bu_select(<32 x i8> %a, <32 x i8> %b) nounwind {406; CHECK-LABEL: xvabsd_bu_select:407; CHECK: # %bb.0:408; CHECK-NEXT: xvabsd.bu $xr0, $xr0, $xr1409; CHECK-NEXT: ret410 %cmp = icmp ult <32 x i8> %a, %b411 %ab = select <32 x i1> %cmp, <32 x i8> %a, <32 x i8> %b412 %ba = select <32 x i1> %cmp, <32 x i8> %b, <32 x i8> %a413 %sub = sub <32 x i8> %ba, %ab414 ret <32 x i8> %sub415}416 417define <16 x i16> @xvabsd_hu_select(<16 x i16> %a, <16 x i16> %b) nounwind {418; CHECK-LABEL: xvabsd_hu_select:419; CHECK: # %bb.0:420; CHECK-NEXT: xvabsd.hu $xr0, $xr0, $xr1421; CHECK-NEXT: ret422 %cmp = icmp ule <16 x i16> %a, %b423 %ab = select <16 x i1> %cmp, <16 x i16> %a, <16 x i16> %b424 %ba = select <16 x i1> %cmp, <16 x i16> %b, <16 x i16> %a425 %sub = sub <16 x i16> %ba, %ab426 ret <16 x i16> %sub427}428 429define <8 x i32> @xvabsd_wu_select(<8 x i32> %a, <8 x i32> %b) nounwind {430; CHECK-LABEL: xvabsd_wu_select:431; CHECK: # %bb.0:432; CHECK-NEXT: xvabsd.wu $xr0, $xr0, $xr1433; CHECK-NEXT: ret434 %cmp = icmp ugt <8 x i32> %a, %b435 %ab = select <8 x i1> %cmp, <8 x i32> %a, <8 x i32> %b436 %ba = select <8 x i1> %cmp, <8 x i32> %b, <8 x i32> %a437 %sub = sub <8 x i32> %ab, %ba438 ret <8 x i32> %sub439}440 441define <4 x i64> @xvabsd_du_select(<4 x i64> %a, <4 x i64> %b) nounwind {442; CHECK-LABEL: xvabsd_du_select:443; CHECK: # %bb.0:444; CHECK-NEXT: xvabsd.du $xr0, $xr0, $xr1445; CHECK-NEXT: ret446 %cmp = icmp uge <4 x i64> %a, %b447 %ab = select <4 x i1> %cmp, <4 x i64> %a, <4 x i64> %b448 %ba = select <4 x i1> %cmp, <4 x i64> %b, <4 x i64> %a449 %sub = sub <4 x i64> %ab, %ba450 ret <4 x i64> %sub451}452 453declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)454 455declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)456declare <32 x i16> @llvm.abs.v32i16(<32 x i16>, i1)457 458declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)459declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)460 461declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)462declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)463 464declare <4 x i128> @llvm.abs.v4i128(<4 x i128>, i1)465 466declare <32 x i8> @llvm.smax.v32i8(<32 x i8>, <32 x i8>)467declare <16 x i16> @llvm.smax.v16i16(<16 x i16>, <16 x i16>)468declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)469declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)470declare <32 x i8> @llvm.smin.v32i8(<32 x i8>, <32 x i8>)471declare <16 x i16> @llvm.smin.v16i16(<16 x i16>, <16 x i16>)472declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)473declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)474declare <32 x i8> @llvm.umax.v32i8(<32 x i8>, <32 x i8>)475declare <16 x i16> @llvm.umax.v16i16(<16 x i16>, <16 x i16>)476declare <8 x i32> @llvm.umax.v8i32(<8 x i32>, <8 x i32>)477declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)478declare <32 x i8> @llvm.umin.v32i8(<32 x i8>, <32 x i8>)479declare <16 x i16> @llvm.umin.v16i16(<16 x i16>, <16 x i16>)480declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)481declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)482