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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5define void @and_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: and_v32i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: xvld $xr0, $a1, 09; CHECK-NEXT: xvld $xr1, $a2, 010; CHECK-NEXT: xvand.v $xr0, $xr0, $xr111; CHECK-NEXT: xvst $xr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <32 x i8>, ptr %a015 %v1 = load <32 x i8>, ptr %a116 %v2 = and <32 x i8> %v0, %v117 store <32 x i8> %v2, ptr %res18 ret void19}20 21define void @and_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {22; CHECK-LABEL: and_v16i16:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: xvld $xr0, $a1, 025; CHECK-NEXT: xvld $xr1, $a2, 026; CHECK-NEXT: xvand.v $xr0, $xr0, $xr127; CHECK-NEXT: xvst $xr0, $a0, 028; CHECK-NEXT: ret29entry:30 %v0 = load <16 x i16>, ptr %a031 %v1 = load <16 x i16>, ptr %a132 %v2 = and <16 x i16> %v0, %v133 store <16 x i16> %v2, ptr %res34 ret void35}36 37define void @and_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {38; CHECK-LABEL: and_v8i32:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: xvld $xr0, $a1, 041; CHECK-NEXT: xvld $xr1, $a2, 042; CHECK-NEXT: xvand.v $xr0, $xr0, $xr143; CHECK-NEXT: xvst $xr0, $a0, 044; CHECK-NEXT: ret45entry:46 %v0 = load <8 x i32>, ptr %a047 %v1 = load <8 x i32>, ptr %a148 %v2 = and <8 x i32> %v0, %v149 store <8 x i32> %v2, ptr %res50 ret void51}52 53define void @and_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {54; CHECK-LABEL: and_v4i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: xvld $xr0, $a1, 057; CHECK-NEXT: xvld $xr1, $a2, 058; CHECK-NEXT: xvand.v $xr0, $xr0, $xr159; CHECK-NEXT: xvst $xr0, $a0, 060; CHECK-NEXT: ret61entry:62 %v0 = load <4 x i64>, ptr %a063 %v1 = load <4 x i64>, ptr %a164 %v2 = and <4 x i64> %v0, %v165 store <4 x i64> %v2, ptr %res66 ret void67}68 69define void @and_u_v32i8(ptr %res, ptr %a0) nounwind {70; CHECK-LABEL: and_u_v32i8:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: xvld $xr0, $a1, 073; CHECK-NEXT: xvandi.b $xr0, $xr0, 3174; CHECK-NEXT: xvst $xr0, $a0, 075; CHECK-NEXT: ret76entry:77 %v0 = load <32 x i8>, ptr %a078 %v1 = and <32 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>79 store <32 x i8> %v1, ptr %res80 ret void81}82 83define void @and_u_v16i16(ptr %res, ptr %a0) nounwind {84; CHECK-LABEL: and_u_v16i16:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: xvld $xr0, $a1, 087; CHECK-NEXT: xvrepli.h $xr1, 3188; CHECK-NEXT: xvand.v $xr0, $xr0, $xr189; CHECK-NEXT: xvst $xr0, $a0, 090; CHECK-NEXT: ret91entry:92 %v0 = load <16 x i16>, ptr %a093 %v1 = and <16 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>94 store <16 x i16> %v1, ptr %res95 ret void96}97 98define void @and_u_v8i32(ptr %res, ptr %a0) nounwind {99; CHECK-LABEL: and_u_v8i32:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: xvld $xr0, $a1, 0102; CHECK-NEXT: xvrepli.w $xr1, 31103; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1104; CHECK-NEXT: xvst $xr0, $a0, 0105; CHECK-NEXT: ret106entry:107 %v0 = load <8 x i32>, ptr %a0108 %v1 = and <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>109 store <8 x i32> %v1, ptr %res110 ret void111}112 113define void @and_u_v4i64(ptr %res, ptr %a0) nounwind {114; CHECK-LABEL: and_u_v4i64:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: xvld $xr0, $a1, 0117; CHECK-NEXT: xvrepli.d $xr1, 31118; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1119; CHECK-NEXT: xvst $xr0, $a0, 0120; CHECK-NEXT: ret121entry:122 %v0 = load <4 x i64>, ptr %a0123 %v1 = and <4 x i64> %v0, <i64 31, i64 31, i64 31, i64 31>124 store <4 x i64> %v1, ptr %res125 ret void126}127