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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5define void @sub_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: sub_v32i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: xvld $xr0, $a1, 09; CHECK-NEXT: xvld $xr1, $a2, 010; CHECK-NEXT: xvsub.b $xr0, $xr0, $xr111; CHECK-NEXT: xvst $xr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <32 x i8>, ptr %a015 %v1 = load <32 x i8>, ptr %a116 %v2 = sub <32 x i8> %v0, %v117 store <32 x i8> %v2, ptr %res18 ret void19}20 21define void @sub_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {22; CHECK-LABEL: sub_v16i16:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: xvld $xr0, $a1, 025; CHECK-NEXT: xvld $xr1, $a2, 026; CHECK-NEXT: xvsub.h $xr0, $xr0, $xr127; CHECK-NEXT: xvst $xr0, $a0, 028; CHECK-NEXT: ret29entry:30 %v0 = load <16 x i16>, ptr %a031 %v1 = load <16 x i16>, ptr %a132 %v2 = sub <16 x i16> %v0, %v133 store <16 x i16> %v2, ptr %res34 ret void35}36 37define void @sub_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {38; CHECK-LABEL: sub_v8i32:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: xvld $xr0, $a1, 041; CHECK-NEXT: xvld $xr1, $a2, 042; CHECK-NEXT: xvsub.w $xr0, $xr0, $xr143; CHECK-NEXT: xvst $xr0, $a0, 044; CHECK-NEXT: ret45entry:46 %v0 = load <8 x i32>, ptr %a047 %v1 = load <8 x i32>, ptr %a148 %v2 = sub <8 x i32> %v0, %v149 store <8 x i32> %v2, ptr %res50 ret void51}52 53define void @sub_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {54; CHECK-LABEL: sub_v4i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: xvld $xr0, $a1, 057; CHECK-NEXT: xvld $xr1, $a2, 058; CHECK-NEXT: xvsub.d $xr0, $xr0, $xr159; CHECK-NEXT: xvst $xr0, $a0, 060; CHECK-NEXT: ret61entry:62 %v0 = load <4 x i64>, ptr %a063 %v1 = load <4 x i64>, ptr %a164 %v2 = sub <4 x i64> %v0, %v165 store <4 x i64> %v2, ptr %res66 ret void67}68 69define void @sub_v32i8_31(ptr %res, ptr %a0) nounwind {70; CHECK-LABEL: sub_v32i8_31:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: xvld $xr0, $a1, 073; CHECK-NEXT: xvsubi.bu $xr0, $xr0, 3174; CHECK-NEXT: xvst $xr0, $a0, 075; CHECK-NEXT: ret76entry:77 %v0 = load <32 x i8>, ptr %a078 %v1 = sub <32 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>79 store <32 x i8> %v1, ptr %res80 ret void81}82 83define void @sub_v16i16_31(ptr %res, ptr %a0) nounwind {84; CHECK-LABEL: sub_v16i16_31:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: xvld $xr0, $a1, 087; CHECK-NEXT: xvsubi.hu $xr0, $xr0, 3188; CHECK-NEXT: xvst $xr0, $a0, 089; CHECK-NEXT: ret90entry:91 %v0 = load <16 x i16>, ptr %a092 %v1 = sub <16 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>93 store <16 x i16> %v1, ptr %res94 ret void95}96 97define void @sub_v8i32_31(ptr %res, ptr %a0) nounwind {98; CHECK-LABEL: sub_v8i32_31:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: xvld $xr0, $a1, 0101; CHECK-NEXT: xvsubi.wu $xr0, $xr0, 31102; CHECK-NEXT: xvst $xr0, $a0, 0103; CHECK-NEXT: ret104entry:105 %v0 = load <8 x i32>, ptr %a0106 %v1 = sub <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>107 store <8 x i32> %v1, ptr %res108 ret void109}110 111define void @sub_v4i64_31(ptr %res, ptr %a0) nounwind {112; CHECK-LABEL: sub_v4i64_31:113; CHECK: # %bb.0: # %entry114; CHECK-NEXT: xvld $xr0, $a1, 0115; CHECK-NEXT: xvsubi.du $xr0, $xr0, 31116; CHECK-NEXT: xvst $xr0, $a0, 0117; CHECK-NEXT: ret118entry:119 %v0 = load <4 x i64>, ptr %a0120 %v1 = sub <4 x i64> %v0, <i64 31, i64 31, i64 31, i64 31>121 store <4 x i64> %v1, ptr %res122 ret void123}124