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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5define void @mulhs_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: mulhs_v32i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: xvld $xr0, $a1, 09; CHECK-NEXT: xvld $xr1, $a2, 010; CHECK-NEXT: xvmuh.b $xr0, $xr0, $xr111; CHECK-NEXT: xvst $xr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <32 x i8>, ptr %a015 %v1 = load <32 x i8>, ptr %a116 %v0s = sext <32 x i8> %v0 to <32 x i16>17 %v1s = sext <32 x i8> %v1 to <32 x i16>18 %m = mul <32 x i16> %v0s, %v1s19 %s = ashr <32 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>20 %v2 = trunc <32 x i16> %s to <32 x i8>21 store <32 x i8> %v2, ptr %res22 ret void23}24 25define void @mulhu_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {26; CHECK-LABEL: mulhu_v32i8:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: xvld $xr0, $a1, 029; CHECK-NEXT: xvld $xr1, $a2, 030; CHECK-NEXT: xvmuh.bu $xr0, $xr0, $xr131; CHECK-NEXT: xvst $xr0, $a0, 032; CHECK-NEXT: ret33entry:34 %v0 = load <32 x i8>, ptr %a035 %v1 = load <32 x i8>, ptr %a136 %v0z = zext <32 x i8> %v0 to <32 x i16>37 %v1z = zext <32 x i8> %v1 to <32 x i16>38 %m = mul <32 x i16> %v0z, %v1z39 %s = lshr <32 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>40 %v2 = trunc <32 x i16> %s to <32 x i8>41 store <32 x i8> %v2, ptr %res42 ret void43}44 45define void @mulhs_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {46; CHECK-LABEL: mulhs_v16i16:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: xvld $xr0, $a1, 049; CHECK-NEXT: xvld $xr1, $a2, 050; CHECK-NEXT: xvmuh.h $xr0, $xr0, $xr151; CHECK-NEXT: xvst $xr0, $a0, 052; CHECK-NEXT: ret53entry:54 %v0 = load <16 x i16>, ptr %a055 %v1 = load <16 x i16>, ptr %a156 %v0s = sext <16 x i16> %v0 to <16 x i32>57 %v1s = sext <16 x i16> %v1 to <16 x i32>58 %m = mul <16 x i32> %v0s, %v1s59 %s = ashr <16 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>60 %v2 = trunc <16 x i32> %s to <16 x i16>61 store <16 x i16> %v2, ptr %res62 ret void63}64 65define void @mulhu_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {66; CHECK-LABEL: mulhu_v16i16:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: xvld $xr0, $a1, 069; CHECK-NEXT: xvld $xr1, $a2, 070; CHECK-NEXT: xvmuh.hu $xr0, $xr0, $xr171; CHECK-NEXT: xvst $xr0, $a0, 072; CHECK-NEXT: ret73entry:74 %v0 = load <16 x i16>, ptr %a075 %v1 = load <16 x i16>, ptr %a176 %v0z = zext <16 x i16> %v0 to <16 x i32>77 %v1z = zext <16 x i16> %v1 to <16 x i32>78 %m = mul <16 x i32> %v0z, %v1z79 %s = lshr <16 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>80 %v2 = trunc <16 x i32> %s to <16 x i16>81 store <16 x i16> %v2, ptr %res82 ret void83}84 85define void @mulhs_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {86; CHECK-LABEL: mulhs_v8i32:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: xvld $xr0, $a1, 089; CHECK-NEXT: xvld $xr1, $a2, 090; CHECK-NEXT: xvmuh.w $xr0, $xr0, $xr191; CHECK-NEXT: xvst $xr0, $a0, 092; CHECK-NEXT: ret93entry:94 %v0 = load <8 x i32>, ptr %a095 %v1 = load <8 x i32>, ptr %a196 %v0s = sext <8 x i32> %v0 to <8 x i64>97 %v1s = sext <8 x i32> %v1 to <8 x i64>98 %m = mul <8 x i64> %v0s, %v1s99 %s = ashr <8 x i64> %m, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>100 %v2 = trunc <8 x i64> %s to <8 x i32>101 store <8 x i32> %v2, ptr %res102 ret void103}104 105define void @mulhu_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {106; CHECK-LABEL: mulhu_v8i32:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: xvld $xr0, $a1, 0109; CHECK-NEXT: xvld $xr1, $a2, 0110; CHECK-NEXT: xvmuh.wu $xr0, $xr0, $xr1111; CHECK-NEXT: xvst $xr0, $a0, 0112; CHECK-NEXT: ret113entry:114 %v0 = load <8 x i32>, ptr %a0115 %v1 = load <8 x i32>, ptr %a1116 %v0z = zext <8 x i32> %v0 to <8 x i64>117 %v1z = zext <8 x i32> %v1 to <8 x i64>118 %m = mul <8 x i64> %v0z, %v1z119 %s = lshr <8 x i64> %m, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>120 %v2 = trunc <8 x i64> %s to <8 x i32>121 store <8 x i32> %v2, ptr %res122 ret void123}124 125define void @mulhs_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {126; CHECK-LABEL: mulhs_v4i64:127; CHECK: # %bb.0: # %entry128; CHECK-NEXT: xvld $xr0, $a1, 0129; CHECK-NEXT: xvld $xr1, $a2, 0130; CHECK-NEXT: xvmuh.d $xr0, $xr0, $xr1131; CHECK-NEXT: xvst $xr0, $a0, 0132; CHECK-NEXT: ret133entry:134 %v0 = load <4 x i64>, ptr %a0135 %v1 = load <4 x i64>, ptr %a1136 %v0s = sext <4 x i64> %v0 to <4 x i128>137 %v1s = sext <4 x i64> %v1 to <4 x i128>138 %m = mul <4 x i128> %v0s, %v1s139 %s = ashr <4 x i128> %m, <i128 64, i128 64, i128 64, i128 64>140 %v2 = trunc <4 x i128> %s to <4 x i64>141 store <4 x i64> %v2, ptr %res142 ret void143}144 145define void @mulhu_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {146; CHECK-LABEL: mulhu_v4i64:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: xvld $xr0, $a1, 0149; CHECK-NEXT: xvld $xr1, $a2, 0150; CHECK-NEXT: xvmuh.du $xr0, $xr0, $xr1151; CHECK-NEXT: xvst $xr0, $a0, 0152; CHECK-NEXT: ret153entry:154 %v0 = load <4 x i64>, ptr %a0155 %v1 = load <4 x i64>, ptr %a1156 %v0z = zext <4 x i64> %v0 to <4 x i128>157 %v1z = zext <4 x i64> %v1 to <4 x i128>158 %m = mul <4 x i128> %v0z, %v1z159 %s = lshr <4 x i128> %m, <i128 64, i128 64, i128 64, i128 64>160 %v2 = trunc <4 x i128> %s to <4 x i64>161 store <4 x i64> %v2, ptr %res162 ret void163}164