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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA644 5define void @vec_reduce_and_v32i8(ptr %src, ptr %dst) nounwind {6; CHECK-LABEL: vec_reduce_and_v32i8:7; CHECK: # %bb.0:8; CHECK-NEXT: xvld $xr0, $a0, 09; CHECK-NEXT: xvpermi.q $xr1, $xr0, 110; CHECK-NEXT: vand.v $vr0, $vr0, $vr111; CHECK-NEXT: vbsrl.v $vr1, $vr0, 812; CHECK-NEXT: vand.v $vr0, $vr1, $vr013; CHECK-NEXT: vbsrl.v $vr1, $vr0, 414; CHECK-NEXT: vand.v $vr0, $vr1, $vr015; CHECK-NEXT: vbsrl.v $vr1, $vr0, 216; CHECK-NEXT: vand.v $vr0, $vr1, $vr017; CHECK-NEXT: vbsrl.v $vr1, $vr0, 118; CHECK-NEXT: vand.v $vr0, $vr1, $vr019; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 020; CHECK-NEXT: ret21 %v = load <32 x i8>, ptr %src22 %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)23 store i8 %res, ptr %dst24 ret void25}26 27define void @vec_reduce_and_v16i16(ptr %src, ptr %dst) nounwind {28; CHECK-LABEL: vec_reduce_and_v16i16:29; CHECK: # %bb.0:30; CHECK-NEXT: xvld $xr0, $a0, 031; CHECK-NEXT: xvpermi.q $xr1, $xr0, 132; CHECK-NEXT: vand.v $vr0, $vr0, $vr133; CHECK-NEXT: vbsrl.v $vr1, $vr0, 834; CHECK-NEXT: vand.v $vr0, $vr1, $vr035; CHECK-NEXT: vbsrl.v $vr1, $vr0, 436; CHECK-NEXT: vand.v $vr0, $vr1, $vr037; CHECK-NEXT: vbsrl.v $vr1, $vr0, 238; CHECK-NEXT: vand.v $vr0, $vr1, $vr039; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 040; CHECK-NEXT: ret41 %v = load <16 x i16>, ptr %src42 %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)43 store i16 %res, ptr %dst44 ret void45}46 47define void @vec_reduce_and_v8i32(ptr %src, ptr %dst) nounwind {48; LA32-LABEL: vec_reduce_and_v8i32:49; LA32: # %bb.0:50; LA32-NEXT: xvld $xr0, $a0, 051; LA32-NEXT: xvpermi.q $xr1, $xr0, 152; LA32-NEXT: vand.v $vr0, $vr0, $vr153; LA32-NEXT: vbsrl.v $vr1, $vr0, 854; LA32-NEXT: vand.v $vr0, $vr1, $vr055; LA32-NEXT: vbsrl.v $vr1, $vr0, 456; LA32-NEXT: vand.v $vr0, $vr1, $vr057; LA32-NEXT: vpickve2gr.w $a0, $vr0, 058; LA32-NEXT: st.w $a0, $a1, 059; LA32-NEXT: ret60;61; LA64-LABEL: vec_reduce_and_v8i32:62; LA64: # %bb.0:63; LA64-NEXT: xvld $xr0, $a0, 064; LA64-NEXT: xvpermi.q $xr1, $xr0, 165; LA64-NEXT: vand.v $vr0, $vr0, $vr166; LA64-NEXT: vbsrl.v $vr1, $vr0, 867; LA64-NEXT: vand.v $vr0, $vr1, $vr068; LA64-NEXT: vbsrl.v $vr1, $vr0, 469; LA64-NEXT: vand.v $vr0, $vr1, $vr070; LA64-NEXT: vstelm.w $vr0, $a1, 0, 071; LA64-NEXT: ret72 %v = load <8 x i32>, ptr %src73 %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)74 store i32 %res, ptr %dst75 ret void76}77 78define void @vec_reduce_and_v4i64(ptr %src, ptr %dst) nounwind {79; LA32-LABEL: vec_reduce_and_v4i64:80; LA32: # %bb.0:81; LA32-NEXT: xvld $xr0, $a0, 082; LA32-NEXT: xvpermi.q $xr1, $xr0, 183; LA32-NEXT: vand.v $vr0, $vr0, $vr184; LA32-NEXT: vpickve2gr.w $a0, $vr0, 285; LA32-NEXT: vpickve2gr.w $a2, $vr0, 086; LA32-NEXT: and $a0, $a2, $a087; LA32-NEXT: vpickve2gr.w $a2, $vr0, 388; LA32-NEXT: vpickve2gr.w $a3, $vr0, 189; LA32-NEXT: and $a2, $a3, $a290; LA32-NEXT: st.w $a2, $a1, 491; LA32-NEXT: st.w $a0, $a1, 092; LA32-NEXT: ret93;94; LA64-LABEL: vec_reduce_and_v4i64:95; LA64: # %bb.0:96; LA64-NEXT: xvld $xr0, $a0, 097; LA64-NEXT: xvpermi.q $xr1, $xr0, 198; LA64-NEXT: vand.v $vr0, $vr0, $vr199; LA64-NEXT: vbsrl.v $vr1, $vr0, 8100; LA64-NEXT: vand.v $vr0, $vr1, $vr0101; LA64-NEXT: vstelm.d $vr0, $a1, 0, 0102; LA64-NEXT: ret103 %v = load <4 x i64>, ptr %src104 %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)105 store i64 %res, ptr %dst106 ret void107}108 109