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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s4 5define void @select_v32i8_imm(ptr %res, ptr %a0) nounwind {6; CHECK-LABEL: select_v32i8_imm:7; CHECK: # %bb.0:8; CHECK-NEXT: xvld $xr0, $a1, 09; CHECK-NEXT: xvrepli.h $xr1, -25610; CHECK-NEXT: xvbitseli.b $xr1, $xr0, 111; CHECK-NEXT: xvst $xr1, $a0, 012; CHECK-NEXT: ret13 %v0 = load <32 x i8>, ptr %a014 %sel = select <32 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> %v015 store <32 x i8> %sel, ptr %res16 ret void17}18 19define void @select_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {20; CHECK-LABEL: select_v32i8:21; CHECK: # %bb.0:22; CHECK-NEXT: xvld $xr0, $a1, 023; CHECK-NEXT: xvld $xr1, $a2, 024; CHECK-NEXT: xvrepli.h $xr2, -25625; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr226; CHECK-NEXT: xvst $xr0, $a0, 027; CHECK-NEXT: ret28 %v0 = load <32 x i8>, ptr %a029 %v1 = load <32 x i8>, ptr %a130 %sel = select <32 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <32 x i8> %v0, <32 x i8> %v131 store <32 x i8> %sel, ptr %res32 ret void33}34 35define void @select_v32i8_1(ptr %res, ptr %a0, ptr %a1) nounwind {36; CHECK-LABEL: select_v32i8_1:37; CHECK: # %bb.0:38; CHECK-NEXT: xvld $xr0, $a1, 039; CHECK-NEXT: xvld $xr1, $a2, 040; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI2_0)41; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI2_0)42; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr243; CHECK-NEXT: xvst $xr0, $a0, 044; CHECK-NEXT: ret45 %v0 = load <32 x i8>, ptr %a046 %v1 = load <32 x i8>, ptr %a147 %sel = select <32 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i8> %v0, <32 x i8> %v148 store <32 x i8> %sel, ptr %res49 ret void50}51 52define void @select_v32i8_2(ptr %res, ptr %a0, ptr %a1) nounwind {53; CHECK-LABEL: select_v32i8_2:54; CHECK: # %bb.0:55; CHECK-NEXT: xvld $xr0, $a1, 056; CHECK-NEXT: xvld $xr1, $a2, 057; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)58; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI3_0)59; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr260; CHECK-NEXT: xvst $xr0, $a0, 061; CHECK-NEXT: ret62 %v0 = load <32 x i8>, ptr %a063 %v1 = load <32 x i8>, ptr %a164 %sel = select <32 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <32 x i8> %v0, <32 x i8> %v165 store <32 x i8> %sel, ptr %res66 ret void67}68 69define void @select_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {70; CHECK-LABEL: select_v16i16:71; CHECK: # %bb.0:72; CHECK-NEXT: xvld $xr0, $a1, 073; CHECK-NEXT: xvld $xr1, $a2, 074; CHECK-NEXT: lu12i.w $a1, -1675; CHECK-NEXT: xvreplgr2vr.w $xr2, $a176; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr277; CHECK-NEXT: xvst $xr0, $a0, 078; CHECK-NEXT: ret79 %v0 = load <16 x i16>, ptr %a080 %v1 = load <16 x i16>, ptr %a181 %sel = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i16> %v0, <16 x i16> %v182 store <16 x i16> %sel, ptr %res83 ret void84}85 86define void @select_v16i16_1(ptr %res, ptr %a0, ptr %a1) nounwind {87; CHECK-LABEL: select_v16i16_1:88; CHECK: # %bb.0:89; CHECK-NEXT: xvld $xr0, $a1, 090; CHECK-NEXT: xvld $xr1, $a2, 091; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI5_0)92; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI5_0)93; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr294; CHECK-NEXT: xvst $xr0, $a0, 095; CHECK-NEXT: ret96 %v0 = load <16 x i16>, ptr %a097 %v1 = load <16 x i16>, ptr %a198 %sel = select <16 x i1> <i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i16> %v0, <16 x i16> %v199 store <16 x i16> %sel, ptr %res100 ret void101}102 103define void @select_v16i16_2(ptr %res, ptr %a0, ptr %a1) nounwind {104; CHECK-LABEL: select_v16i16_2:105; CHECK: # %bb.0:106; CHECK-NEXT: xvld $xr0, $a1, 0107; CHECK-NEXT: xvld $xr1, $a2, 0108; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI6_0)109; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI6_0)110; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2111; CHECK-NEXT: xvst $xr0, $a0, 0112; CHECK-NEXT: ret113 %v0 = load <16 x i16>, ptr %a0114 %v1 = load <16 x i16>, ptr %a1115 %sel = select <16 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <16 x i16> %v0, <16 x i16> %v1116 store <16 x i16> %sel, ptr %res117 ret void118}119 120define void @select_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {121; CHECK-LABEL: select_v8i32:122; CHECK: # %bb.0:123; CHECK-NEXT: xvld $xr0, $a1, 0124; CHECK-NEXT: xvld $xr1, $a2, 0125; CHECK-NEXT: xvldi $xr2, -1552126; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2127; CHECK-NEXT: xvst $xr0, $a0, 0128; CHECK-NEXT: ret129 %v0 = load <8 x i32>, ptr %a0130 %v1 = load <8 x i32>, ptr %a1131 %sel = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i32> %v0, <8 x i32> %v1132 store <8 x i32> %sel, ptr %res133 ret void134}135 136define void @select_v8i32_1(ptr %res, ptr %a0, ptr %a1) nounwind {137; CHECK-LABEL: select_v8i32_1:138; CHECK: # %bb.0:139; CHECK-NEXT: xvld $xr0, $a1, 0140; CHECK-NEXT: xvld $xr1, $a2, 0141; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI8_0)142; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI8_0)143; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2144; CHECK-NEXT: xvst $xr0, $a0, 0145; CHECK-NEXT: ret146 %v0 = load <8 x i32>, ptr %a0147 %v1 = load <8 x i32>, ptr %a1148 %sel = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i32> %v0, <8 x i32> %v1149 store <8 x i32> %sel, ptr %res150 ret void151}152 153define void @select_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {154; CHECK-LABEL: select_v8f32:155; CHECK: # %bb.0:156; CHECK-NEXT: xvld $xr0, $a1, 0157; CHECK-NEXT: xvld $xr1, $a2, 0158; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)159; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI9_0)160; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2161; CHECK-NEXT: xvst $xr0, $a0, 0162; CHECK-NEXT: ret163 %v0 = load <8 x float>, ptr %a0164 %v1 = load <8 x float>, ptr %a1165 %sel = select <8 x i1> <i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false>, <8 x float> %v0, <8 x float> %v1166 store <8 x float> %sel, ptr %res167 ret void168}169 170define void @select_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {171; CHECK-LABEL: select_v4i64:172; CHECK: # %bb.0:173; CHECK-NEXT: xvld $xr0, $a1, 0174; CHECK-NEXT: xvld $xr1, $a2, 0175; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI10_0)176; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI10_0)177; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2178; CHECK-NEXT: xvst $xr0, $a0, 0179; CHECK-NEXT: ret180 %v0 = load <4 x i64>, ptr %a0181 %v1 = load <4 x i64>, ptr %a1182 %sel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v0, <4 x i64> %v1183 store <4 x i64> %sel, ptr %res184 ret void185}186 187define void @select_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {188; CHECK-LABEL: select_v4f64:189; CHECK: # %bb.0:190; CHECK-NEXT: xvld $xr0, $a1, 0191; CHECK-NEXT: xvld $xr1, $a2, 0192; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)193; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI11_0)194; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2195; CHECK-NEXT: xvst $xr0, $a0, 0196; CHECK-NEXT: ret197 %v0 = load <4 x double>, ptr %a0198 %v1 = load <4 x double>, ptr %a1199 %sel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v0, <4 x double> %v1200 store <4 x double> %sel, ptr %res201 ret void202}203