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1; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=-relax \2; RUN: --relocation-model=pic --code-model=medium < %s \3; RUN: | llvm-readobj -r - | FileCheck --check-prefix=CHECK-RELOC %s4; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=+relax \5; RUN: --relocation-model=pic --code-model=medium < %s \6; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK-RELOC,RELAX %s7 8; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=-relax --enable-tlsdesc \9; RUN: --relocation-model=pic --code-model=medium < %s \10; RUN: | llvm-readobj -r - | FileCheck --check-prefix=DESC-RELOC %s11; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=+relax --enable-tlsdesc \12; RUN: --relocation-model=pic --code-model=medium < %s \13; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=DESC-RELOC,DESC-RELAX %s14 15;; Check relocations when disable or enable linker relaxation.16;; This tests are also able to test for removing relax mask flags17;; after loongarch-merge-base-offset pass because no relax relocs18;; are emitted after being optimized by it.19 20@g_e = external global i3221@g_i = internal global i32 022@g_i1 = internal global i32 123@t_un = external thread_local global i3224@t_ld = external thread_local(localdynamic) global i3225@t_ie = external thread_local(initialexec) global i3226@t_le = external thread_local(localexec) global i3227 28declare void @callee1() nounwind29declare dso_local void @callee2() nounwind30declare dso_local void @callee3() nounwind31 32; CHECK-RELOC: R_LARCH_GOT_PC_HI20 g_e 0x033; RELAX: R_LARCH_RELAX - 0x034; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 g_e 0x035; RELAX-NEXT: R_LARCH_RELAX - 0x036; CHECK-RELOC-NEXT: R_LARCH_PCALA_HI20 g_i 0x037; CHECK-RELOC-NEXT: R_LARCH_PCALA_LO12 g_i 0x038; CHECK-RELOC: R_LARCH_TLS_GD_PC_HI20 t_un 0x039; RELAX-NEXT: R_LARCH_RELAX - 0x040; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 t_un 0x041; RELAX-NEXT: R_LARCH_RELAX - 0x042; CHECK-RELOC-NEXT: R_LARCH_CALL36 __tls_get_addr 0x043; RELAX-NEXT: R_LARCH_RELAX - 0x044; DESC-RELOC: R_LARCH_TLS_DESC_PC_HI20 t_un 0x045; DESC-RELAX: R_LARCH_RELAX - 0x046; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_LO12 t_un 0x047; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x048; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_LD t_un 0x049; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x050; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_CALL t_un 0x051; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x052; CHECK-RELOC-NEXT: R_LARCH_TLS_LD_PC_HI20 t_ld 0x053; RELAX-NEXT: R_LARCH_RELAX - 0x054; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 t_ld 0x055; RELAX-NEXT: R_LARCH_RELAX - 0x056; CHECK-RELOC-NEXT: R_LARCH_CALL36 __tls_get_addr 0x057; RELAX-NEXT: R_LARCH_RELAX - 0x058; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_HI20 t_ld 0x059; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x060; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_LO12 t_ld 0x061; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x062; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_LD t_ld 0x063; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x064; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_CALL t_ld 0x065; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x066; CHECK-RELOC-NEXT: R_LARCH_TLS_IE_PC_HI20 t_ie 0x067; RELAX-NEXT: R_LARCH_RELAX - 0x068; CHECK-RELOC-NEXT: R_LARCH_TLS_IE_PC_LO12 t_ie 0x069; RELAX-NEXT: R_LARCH_RELAX - 0x070; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_HI20_R t_le 0x071; RELAX-NEXT: R_LARCH_RELAX - 0x072; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_ADD_R t_le 0x073; RELAX-NEXT: R_LARCH_RELAX - 0x074; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_LO12_R t_le 0x075; RELAX-NEXT: R_LARCH_RELAX - 0x076; CHECK-RELOC-NEXT: R_LARCH_PCALA_HI20 g_i1 0x077; RELAX-NEXT: R_LARCH_RELAX - 0x078; CHECK-RELOC-NEXT: R_LARCH_PCALA_LO12 g_i1 0x079; RELAX-NEXT: R_LARCH_RELAX - 0x080; RELAX-NEXT: R_LARCH_ALIGN - 0x1C81; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee1 0x082; RELAX-NEXT: R_LARCH_RELAX - 0x083; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee2 0x084; RELAX-NEXT: R_LARCH_RELAX - 0x085; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee3 0x086; RELAX-NEXT: R_LARCH_RELAX - 0x087 88;; No ALIGN reloc will emit before the first linker-relaxable instruction.89define ptr @loader() nounwind {90 %a = load volatile i32, ptr @g_e91 %b = load volatile i32, ptr @g_i92 %c = load volatile i32, ptr @t_un93 %d = load volatile i32, ptr @t_ld94 %e = load volatile i32, ptr @t_ie95 %f = load volatile i32, ptr @t_le96 ret ptr @g_i197}98 99;; ALIGN reloc will be emitted here.100define void @caller() nounwind {101 call i32 @callee1()102 call i32 @callee2()103 tail call i32 @callee3()104 ret void105}106