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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind {6; CHECK-LABEL: buildvector_v16i8_splat:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vreplgr2vr.b $vr0, $a19; CHECK-NEXT: vst $vr0, $a0, 010; CHECK-NEXT: ret11entry:12 %insert = insertelement <16 x i8> undef, i8 %a0, i8 013 %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer14 store <16 x i8> %splat, ptr %dst15 ret void16}17 18define void @buildvector_v8i16_splat(ptr %dst, i16 %a0) nounwind {19; CHECK-LABEL: buildvector_v8i16_splat:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vreplgr2vr.h $vr0, $a122; CHECK-NEXT: vst $vr0, $a0, 023; CHECK-NEXT: ret24entry:25 %insert = insertelement <8 x i16> undef, i16 %a0, i8 026 %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer27 store <8 x i16> %splat, ptr %dst28 ret void29}30 31define void @buildvector_v4i32_splat(ptr %dst, i32 %a0) nounwind {32; CHECK-LABEL: buildvector_v4i32_splat:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vreplgr2vr.w $vr0, $a135; CHECK-NEXT: vst $vr0, $a0, 036; CHECK-NEXT: ret37entry:38 %insert = insertelement <4 x i32> undef, i32 %a0, i8 039 %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer40 store <4 x i32> %splat, ptr %dst41 ret void42}43 44define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind {45; LA32-LABEL: buildvector_v2i64_splat:46; LA32: # %bb.0: # %entry47; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 048; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 149; LA32-NEXT: vreplvei.d $vr0, $vr0, 050; LA32-NEXT: vst $vr0, $a0, 051; LA32-NEXT: ret52;53; LA64-LABEL: buildvector_v2i64_splat:54; LA64: # %bb.0: # %entry55; LA64-NEXT: vreplgr2vr.d $vr0, $a156; LA64-NEXT: vst $vr0, $a0, 057; LA64-NEXT: ret58entry:59 %insert = insertelement <2 x i64> undef, i64 %a0, i8 060 %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer61 store <2 x i64> %splat, ptr %dst62 ret void63}64 65define void @buildvector_v4f32_splat(ptr %dst, float %a0) nounwind {66; CHECK-LABEL: buildvector_v4f32_splat:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr069; CHECK-NEXT: vreplvei.w $vr0, $vr0, 070; CHECK-NEXT: vst $vr0, $a0, 071; CHECK-NEXT: ret72entry:73 %insert = insertelement <4 x float> undef, float %a0, i8 074 %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer75 store <4 x float> %splat, ptr %dst76 ret void77}78 79define void @buildvector_v2f64_splat(ptr %dst, double %a0) nounwind {80; CHECK-LABEL: buildvector_v2f64_splat:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr083; CHECK-NEXT: vreplvei.d $vr0, $vr0, 084; CHECK-NEXT: vst $vr0, $a0, 085; CHECK-NEXT: ret86entry:87 %insert = insertelement <2 x double> undef, double %a0, i8 088 %splat = shufflevector <2 x double> %insert, <2 x double> undef, <2 x i32> zeroinitializer89 store <2 x double> %splat, ptr %dst90 ret void91}92 93define void @buildvector_v16i8_const_splat(ptr %dst) nounwind {94; CHECK-LABEL: buildvector_v16i8_const_splat:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vrepli.b $vr0, 197; CHECK-NEXT: vst $vr0, $a0, 098; CHECK-NEXT: ret99entry:100 store <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, ptr %dst101 ret void102}103 104define void @buildvector_v16i8_const_splat_v2i64(ptr %dst) nounwind {105; LA32-LABEL: buildvector_v16i8_const_splat_v2i64:106; LA32: # %bb.0: # %entry107; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)108; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI7_0)109; LA32-NEXT: vst $vr0, $a0, 0110; LA32-NEXT: ret111;112; LA64-LABEL: buildvector_v16i8_const_splat_v2i64:113; LA64: # %bb.0: # %entry114; LA64-NEXT: lu12i.w $a1, 7115; LA64-NEXT: ori $a1, $a1, 3453116; LA64-NEXT: vreplgr2vr.d $vr0, $a1117; LA64-NEXT: vst $vr0, $a0, 0118; LA64-NEXT: ret119entry:120 store <16 x i8> <i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, ptr %dst121 ret void122}123 124define void @buildvector_v8i16_const_splat(ptr %dst) nounwind {125; CHECK-LABEL: buildvector_v8i16_const_splat:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: vrepli.h $vr0, 1128; CHECK-NEXT: vst $vr0, $a0, 0129; CHECK-NEXT: ret130entry:131 store <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, ptr %dst132 ret void133}134 135define void @buildvector_v8i16_const_splat_v2i64(ptr %dst) nounwind {136; LA32-LABEL: buildvector_v8i16_const_splat_v2i64:137; LA32: # %bb.0: # %entry138; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)139; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI9_0)140; LA32-NEXT: vst $vr0, $a0, 0141; LA32-NEXT: ret142;143; LA64-LABEL: buildvector_v8i16_const_splat_v2i64:144; LA64: # %bb.0: # %entry145; LA64-NEXT: ori $a1, $zero, 512146; LA64-NEXT: vreplgr2vr.d $vr0, $a1147; LA64-NEXT: vst $vr0, $a0, 0148; LA64-NEXT: ret149entry:150 store <8 x i16> <i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0>, ptr %dst151 ret void152}153 154define void @buildvector_v4i32_const_splat(ptr %dst) nounwind {155; CHECK-LABEL: buildvector_v4i32_const_splat:156; CHECK: # %bb.0: # %entry157; CHECK-NEXT: vrepli.w $vr0, 1158; CHECK-NEXT: vst $vr0, $a0, 0159; CHECK-NEXT: ret160entry:161 store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %dst162 ret void163}164 165define void @buildvector_v4i32_const_splat_v2i64(ptr %dst) nounwind {166; LA32-LABEL: buildvector_v4i32_const_splat_v2i64:167; LA32: # %bb.0: # %entry168; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)169; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)170; LA32-NEXT: vst $vr0, $a0, 0171; LA32-NEXT: ret172;173; LA64-LABEL: buildvector_v4i32_const_splat_v2i64:174; LA64: # %bb.0: # %entry175; LA64-NEXT: ori $a1, $zero, 512176; LA64-NEXT: vreplgr2vr.d $vr0, $a1177; LA64-NEXT: vst $vr0, $a0, 0178; LA64-NEXT: ret179entry:180 store <4 x i32> <i32 512, i32 0, i32 512, i32 0>, ptr %dst181 ret void182}183 184define void @buildvector_v2i64_const_splat(ptr %dst) nounwind {185; CHECK-LABEL: buildvector_v2i64_const_splat:186; CHECK: # %bb.0: # %entry187; CHECK-NEXT: vrepli.d $vr0, 1188; CHECK-NEXT: vst $vr0, $a0, 0189; CHECK-NEXT: ret190entry:191 store <2 x i64> <i64 1, i64 1>, ptr %dst192 ret void193}194 195;; Also check buildvector_const_splat_vldi_1010.196define void @buildvector_v4f32_const_splat(ptr %dst) nounwind {197; CHECK-LABEL: buildvector_v4f32_const_splat:198; CHECK: # %bb.0: # %entry199; CHECK-NEXT: vldi $vr0, -1424200; CHECK-NEXT: vst $vr0, $a0, 0201; CHECK-NEXT: ret202entry:203 store <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, ptr %dst204 ret void205}206 207;; Also check buildvector_const_splat_vldi_1100.208define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {209; CHECK-LABEL: buildvector_v2f64_const_splat:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: vldi $vr0, -912212; CHECK-NEXT: vst $vr0, $a0, 0213; CHECK-NEXT: ret214entry:215 store <2 x double> <double 1.0, double 1.0>, ptr %dst216 ret void217}218 219;; imm[11:8] == 4'b0000/4'b0100/4'b1000 can be represented using vrepli.[whb].220define void @buildvector_const_splat_vldi_0001(ptr %dst) nounwind {221; CHECK-LABEL: buildvector_const_splat_vldi_0001:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: vldi $vr0, -3837224; CHECK-NEXT: vst $vr0, $a0, 0225; CHECK-NEXT: ret226entry:227 store <4 x i32> <i32 768, i32 768, i32 768, i32 768>, ptr %dst228 ret void229}230 231define void @buildvector_const_splat_vldi_0010(ptr %dst) nounwind {232; CHECK-LABEL: buildvector_const_splat_vldi_0010:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: vldi $vr0, -3583235; CHECK-NEXT: vst $vr0, $a0, 0236; CHECK-NEXT: ret237entry:238 store <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>, ptr %dst239 ret void240}241 242define void @buildvector_const_splat_vldi_0011(ptr %dst) nounwind {243; CHECK-LABEL: buildvector_const_splat_vldi_0011:244; CHECK: # %bb.0: # %entry245; CHECK-NEXT: vldi $vr0, -3327246; CHECK-NEXT: vst $vr0, $a0, 0247; CHECK-NEXT: ret248entry:249 store <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>, ptr %dst250 ret void251}252 253define void @buildvector_const_splat_vldi_0101(ptr %dst) {254; CHECK-LABEL: buildvector_const_splat_vldi_0101:255; CHECK: # %bb.0: # %entry256; CHECK-NEXT: vldi $vr0, -2813257; CHECK-NEXT: vst $vr0, $a0, 0258; CHECK-NEXT: ret259entry:260 store <8 x i16> <i16 768, i16 768, i16 768, i16 768, i16 768, i16 768, i16 768, i16 768>, ptr %dst261 ret void262}263 264define void @buildvector_const_splat_vldi_0110(ptr %dst) nounwind {265; CHECK-LABEL: buildvector_const_splat_vldi_0110:266; CHECK: # %bb.0: # %entry267; CHECK-NEXT: vldi $vr0, -2557268; CHECK-NEXT: vst $vr0, $a0, 0269; CHECK-NEXT: ret270entry:271 store <4 x i32> <i32 1023, i32 1023, i32 1023, i32 1023>, ptr %dst272 ret void273}274 275define void @buildvector_const_splat_vldi_0111(ptr %dst) nounwind {276; CHECK-LABEL: buildvector_const_splat_vldi_0111:277; CHECK: # %bb.0: # %entry278; CHECK-NEXT: vldi $vr0, -2305279; CHECK-NEXT: vst $vr0, $a0, 0280; CHECK-NEXT: ret281entry:282 store <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>, ptr %dst283 ret void284}285 286define void @buildvector_const_splat_vldi_1001(ptr %dst) nounwind {287; CHECK-LABEL: buildvector_const_splat_vldi_1001:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: vldi $vr0, -1789290; CHECK-NEXT: vst $vr0, $a0, 0291; CHECK-NEXT: ret292entry:293 store <4 x i32> <i32 65535, i32 0, i32 65535, i32 0>, ptr %dst294 ret void295}296 297define void @buildvector_const_splat_vldi_1011(ptr %dst) nounwind {298; CHECK-LABEL: buildvector_const_splat_vldi_1011:299; CHECK: # %bb.0: # %entry300; CHECK-NEXT: vldi $vr0, -1280301; CHECK-NEXT: vst $vr0, $a0, 0302; CHECK-NEXT: ret303entry:304 store <4 x float> <float 2.0, float 0.0, float 2.0, float 0.0>, ptr %dst305 ret void306}307 308define void @buildvector_v16i8_const(ptr %dst) nounwind {309; CHECK-LABEL: buildvector_v16i8_const:310; CHECK: # %bb.0: # %entry311; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI23_0)312; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI23_0)313; CHECK-NEXT: vst $vr0, $a0, 0314; CHECK-NEXT: ret315entry:316 store <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %dst317 ret void318}319 320define void @buildvector_v8i16_const(ptr %dst) nounwind {321; CHECK-LABEL: buildvector_v8i16_const:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI24_0)324; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI24_0)325; CHECK-NEXT: vst $vr0, $a0, 0326; CHECK-NEXT: ret327entry:328 store <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, ptr %dst329 ret void330}331 332define void @buildvector_v4i32_const(ptr %dst) nounwind {333; CHECK-LABEL: buildvector_v4i32_const:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI25_0)336; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI25_0)337; CHECK-NEXT: vst $vr0, $a0, 0338; CHECK-NEXT: ret339entry:340 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %dst341 ret void342}343 344define void @buildvector_v2i64_const(ptr %dst) nounwind {345; CHECK-LABEL: buildvector_v2i64_const:346; CHECK: # %bb.0: # %entry347; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI26_0)348; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI26_0)349; CHECK-NEXT: vst $vr0, $a0, 0350; CHECK-NEXT: ret351entry:352 store <2 x i64> <i64 0, i64 1>, ptr %dst353 ret void354}355 356define void @buildvector_v2f32_const(ptr %dst) nounwind {357; CHECK-LABEL: buildvector_v2f32_const:358; CHECK: # %bb.0: # %entry359; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI27_0)360; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI27_0)361; CHECK-NEXT: vst $vr0, $a0, 0362; CHECK-NEXT: ret363entry:364 store <4 x float> <float 0.0, float 1.0, float 2.0, float 3.0>, ptr %dst365 ret void366}367 368define void @buildvector_v2f64_const(ptr %dst) nounwind {369; CHECK-LABEL: buildvector_v2f64_const:370; CHECK: # %bb.0: # %entry371; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI28_0)372; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI28_0)373; CHECK-NEXT: vst $vr0, $a0, 0374; CHECK-NEXT: ret375entry:376 store <2 x double> <double 0.0, double 1.0>, ptr %dst377 ret void378}379 380define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind {381; LA32-LABEL: buildvector_v16i8:382; LA32: # %bb.0: # %entry383; LA32-NEXT: ld.b $t0, $sp, 32384; LA32-NEXT: ld.b $t1, $sp, 28385; LA32-NEXT: ld.b $t2, $sp, 24386; LA32-NEXT: ld.b $t3, $sp, 20387; LA32-NEXT: ld.b $t4, $sp, 16388; LA32-NEXT: ld.b $t5, $sp, 12389; LA32-NEXT: ld.b $t6, $sp, 8390; LA32-NEXT: ld.b $t7, $sp, 4391; LA32-NEXT: ld.b $t8, $sp, 0392; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0393; LA32-NEXT: vinsgr2vr.b $vr0, $a2, 1394; LA32-NEXT: vinsgr2vr.b $vr0, $a3, 2395; LA32-NEXT: vinsgr2vr.b $vr0, $a4, 3396; LA32-NEXT: vinsgr2vr.b $vr0, $a5, 4397; LA32-NEXT: vinsgr2vr.b $vr0, $a6, 5398; LA32-NEXT: vinsgr2vr.b $vr0, $a7, 6399; LA32-NEXT: vinsgr2vr.b $vr0, $t8, 7400; LA32-NEXT: vinsgr2vr.b $vr0, $t7, 8401; LA32-NEXT: vinsgr2vr.b $vr0, $t6, 9402; LA32-NEXT: vinsgr2vr.b $vr0, $t5, 10403; LA32-NEXT: vinsgr2vr.b $vr0, $t4, 11404; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 12405; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 13406; LA32-NEXT: vinsgr2vr.b $vr0, $t1, 14407; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 15408; LA32-NEXT: vst $vr0, $a0, 0409; LA32-NEXT: ret410;411; LA64-LABEL: buildvector_v16i8:412; LA64: # %bb.0: # %entry413; LA64-NEXT: ld.b $t0, $sp, 64414; LA64-NEXT: ld.b $t1, $sp, 56415; LA64-NEXT: ld.b $t2, $sp, 48416; LA64-NEXT: ld.b $t3, $sp, 40417; LA64-NEXT: ld.b $t4, $sp, 32418; LA64-NEXT: ld.b $t5, $sp, 24419; LA64-NEXT: ld.b $t6, $sp, 16420; LA64-NEXT: ld.b $t7, $sp, 8421; LA64-NEXT: ld.b $t8, $sp, 0422; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0423; LA64-NEXT: vinsgr2vr.b $vr0, $a2, 1424; LA64-NEXT: vinsgr2vr.b $vr0, $a3, 2425; LA64-NEXT: vinsgr2vr.b $vr0, $a4, 3426; LA64-NEXT: vinsgr2vr.b $vr0, $a5, 4427; LA64-NEXT: vinsgr2vr.b $vr0, $a6, 5428; LA64-NEXT: vinsgr2vr.b $vr0, $a7, 6429; LA64-NEXT: vinsgr2vr.b $vr0, $t8, 7430; LA64-NEXT: vinsgr2vr.b $vr0, $t7, 8431; LA64-NEXT: vinsgr2vr.b $vr0, $t6, 9432; LA64-NEXT: vinsgr2vr.b $vr0, $t5, 10433; LA64-NEXT: vinsgr2vr.b $vr0, $t4, 11434; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 12435; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 13436; LA64-NEXT: vinsgr2vr.b $vr0, $t1, 14437; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 15438; LA64-NEXT: vst $vr0, $a0, 0439; LA64-NEXT: ret440entry:441 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0442 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1443 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2444 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3445 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4446 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5447 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6448 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7449 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8450 %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9451 %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10452 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11453 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12454 %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13455 %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14456 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15457 store <16 x i8> %ins15, ptr %dst458 ret void459}460 461define void @buildvector_v16i8_partial(ptr %dst, i8 %a2, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) nounwind {462; CHECK-LABEL: buildvector_v16i8_partial:463; CHECK: # %bb.0: # %entry464; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 2465; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 6466; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 8467; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 11468; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 12469; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 15470; CHECK-NEXT: vst $vr0, $a0, 0471; CHECK-NEXT: ret472entry:473 %ins0 = insertelement <16 x i8> undef, i8 undef, i32 0474 %ins1 = insertelement <16 x i8> %ins0, i8 undef, i32 1475 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2476 %ins3 = insertelement <16 x i8> %ins2, i8 undef, i32 3477 %ins4 = insertelement <16 x i8> %ins3, i8 undef, i32 4478 %ins5 = insertelement <16 x i8> %ins4, i8 undef, i32 5479 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6480 %ins7 = insertelement <16 x i8> %ins6, i8 undef, i32 7481 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8482 %ins9 = insertelement <16 x i8> %ins8, i8 undef, i32 9483 %ins10 = insertelement <16 x i8> %ins9, i8 undef, i32 10484 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11485 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12486 %ins13 = insertelement <16 x i8> %ins12, i8 undef, i32 13487 %ins14 = insertelement <16 x i8> %ins13, i8 undef, i32 14488 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15489 store <16 x i8> %ins15, ptr %dst490 ret void491}492 493define void @buildvector_v16i8_with_constant(ptr %dst, i8 %a0, i8 %a4, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) nounwind {494; CHECK-LABEL: buildvector_v16i8_with_constant:495; CHECK: # %bb.0: # %entry496; CHECK-NEXT: vrepli.b $vr0, 0497; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0498; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 4499; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 6500; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 8501; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 11502; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 12503; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 15504; CHECK-NEXT: vst $vr0, $a0, 0505; CHECK-NEXT: ret506entry:507 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0508 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1509 %ins2 = insertelement <16 x i8> %ins1, i8 0, i32 2510 %ins3 = insertelement <16 x i8> %ins2, i8 0, i32 3511 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4512 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5513 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6514 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7515 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8516 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9517 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10518 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11519 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12520 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13521 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14522 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15523 store <16 x i8> %ins15, ptr %dst524 ret void525}526 527define void @buildvector_v16i8_subseq_2(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7) nounwind {528; CHECK-LABEL: buildvector_v16i8_subseq_2:529; CHECK: # %bb.0: # %entry530; CHECK-NEXT: ld.b $t0, $sp, 0531; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0532; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1533; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2534; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3535; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4536; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5537; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6538; CHECK-NEXT: vinsgr2vr.b $vr0, $t0, 7539; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0540; CHECK-NEXT: vst $vr0, $a0, 0541; CHECK-NEXT: ret542entry:543 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0544 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1545 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2546 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3547 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4548 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5549 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6550 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7551 %ins8 = insertelement <16 x i8> %ins7, i8 %a0, i32 8552 %ins9 = insertelement <16 x i8> %ins8, i8 %a1, i32 9553 %ins10 = insertelement <16 x i8> %ins9, i8 %a2, i32 10554 %ins11 = insertelement <16 x i8> %ins10, i8 %a3, i32 11555 %ins12 = insertelement <16 x i8> %ins11, i8 %a4, i32 12556 %ins13 = insertelement <16 x i8> %ins12, i8 %a5, i32 13557 %ins14 = insertelement <16 x i8> %ins13, i8 %a6, i32 14558 %ins15 = insertelement <16 x i8> %ins14, i8 %a7, i32 15559 store <16 x i8> %ins15, ptr %dst560 ret void561}562 563define void @buildvector_v16i8_subseq_4(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3) nounwind {564; CHECK-LABEL: buildvector_v16i8_subseq_4:565; CHECK: # %bb.0: # %entry566; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0567; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1568; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2569; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3570; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0571; CHECK-NEXT: vst $vr0, $a0, 0572; CHECK-NEXT: ret573entry:574 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0575 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1576 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2577 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3578 %ins4 = insertelement <16 x i8> %ins3, i8 %a0, i32 4579 %ins5 = insertelement <16 x i8> %ins4, i8 %a1, i32 5580 %ins6 = insertelement <16 x i8> %ins5, i8 %a2, i32 6581 %ins7 = insertelement <16 x i8> %ins6, i8 %a3, i32 7582 %ins8 = insertelement <16 x i8> %ins7, i8 %a0, i32 8583 %ins9 = insertelement <16 x i8> %ins8, i8 %a1, i32 9584 %ins10 = insertelement <16 x i8> %ins9, i8 %a2, i32 10585 %ins11 = insertelement <16 x i8> %ins10, i8 %a3, i32 11586 %ins12 = insertelement <16 x i8> %ins11, i8 %a0, i32 12587 %ins13 = insertelement <16 x i8> %ins12, i8 %a1, i32 13588 %ins14 = insertelement <16 x i8> %ins13, i8 %a2, i32 14589 %ins15 = insertelement <16 x i8> %ins14, i8 %a3, i32 15590 store <16 x i8> %ins15, ptr %dst591 ret void592}593 594define void @buildvector_v16i8_subseq_8(ptr %dst, i8 %a0, i8 %a1) nounwind {595; CHECK-LABEL: buildvector_v16i8_subseq_8:596; CHECK: # %bb.0: # %entry597; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0598; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1599; CHECK-NEXT: vreplvei.h $vr0, $vr0, 0600; CHECK-NEXT: vst $vr0, $a0, 0601; CHECK-NEXT: ret602entry:603 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0604 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1605 %ins2 = insertelement <16 x i8> %ins1, i8 %a0, i32 2606 %ins3 = insertelement <16 x i8> %ins2, i8 %a1, i32 3607 %ins4 = insertelement <16 x i8> %ins3, i8 %a0, i32 4608 %ins5 = insertelement <16 x i8> %ins4, i8 %a1, i32 5609 %ins6 = insertelement <16 x i8> %ins5, i8 %a0, i32 6610 %ins7 = insertelement <16 x i8> %ins6, i8 %a1, i32 7611 %ins8 = insertelement <16 x i8> %ins7, i8 %a0, i32 8612 %ins9 = insertelement <16 x i8> %ins8, i8 %a1, i32 9613 %ins10 = insertelement <16 x i8> %ins9, i8 %a0, i32 10614 %ins11 = insertelement <16 x i8> %ins10, i8 %a1, i32 11615 %ins12 = insertelement <16 x i8> %ins11, i8 %a0, i32 12616 %ins13 = insertelement <16 x i8> %ins12, i8 %a1, i32 13617 %ins14 = insertelement <16 x i8> %ins13, i8 %a0, i32 14618 %ins15 = insertelement <16 x i8> %ins14, i8 %a1, i32 15619 store <16 x i8> %ins15, ptr %dst620 ret void621}622 623define void @buildvector_v8i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {624; CHECK-LABEL: buildvector_v8i16:625; CHECK: # %bb.0: # %entry626; CHECK-NEXT: ld.h $t0, $sp, 0627; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0628; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1629; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 2630; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 3631; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 4632; CHECK-NEXT: vinsgr2vr.h $vr0, $a6, 5633; CHECK-NEXT: vinsgr2vr.h $vr0, $a7, 6634; CHECK-NEXT: vinsgr2vr.h $vr0, $t0, 7635; CHECK-NEXT: vst $vr0, $a0, 0636; CHECK-NEXT: ret637entry:638 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0639 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1640 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2641 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3642 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4643 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5644 %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6645 %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7646 store <8 x i16> %ins7, ptr %dst647 ret void648}649 650define void @buildvector_v8i16_partial(ptr %dst, i16 %a1, i16 %a3, i16 %a4, i16 %a5) nounwind {651; CHECK-LABEL: buildvector_v8i16_partial:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 1654; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 3655; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 4656; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 5657; CHECK-NEXT: vst $vr0, $a0, 0658; CHECK-NEXT: ret659entry:660 %ins0 = insertelement <8 x i16> undef, i16 undef, i32 0661 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1662 %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2663 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3664 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4665 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5666 %ins6 = insertelement <8 x i16> %ins5, i16 undef, i32 6667 %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7668 store <8 x i16> %ins7, ptr %dst669 ret void670}671 672define void @buildvector_v8i16_with_constant(ptr %dst, i16 %a0, i16 %a3, i16 %a4, i16 %a5) nounwind {673; CHECK-LABEL: buildvector_v8i16_with_constant:674; CHECK: # %bb.0: # %entry675; CHECK-NEXT: vrepli.b $vr0, 0676; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0677; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 3678; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 4679; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 5680; CHECK-NEXT: vst $vr0, $a0, 0681; CHECK-NEXT: ret682entry:683 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0684 %ins1 = insertelement <8 x i16> %ins0, i16 0, i32 1685 %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2686 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3687 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4688 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5689 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6690 %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7691 store <8 x i16> %ins7, ptr %dst692 ret void693}694 695define void @buildvector_v8i16_subseq_2(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3) nounwind {696; CHECK-LABEL: buildvector_v8i16_subseq_2:697; CHECK: # %bb.0: # %entry698; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0699; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1700; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 2701; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 3702; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0703; CHECK-NEXT: vst $vr0, $a0, 0704; CHECK-NEXT: ret705entry:706 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0707 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1708 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2709 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3710 %ins4 = insertelement <8 x i16> %ins3, i16 %a0, i32 4711 %ins5 = insertelement <8 x i16> %ins4, i16 %a1, i32 5712 %ins6 = insertelement <8 x i16> %ins5, i16 %a2, i32 6713 %ins7 = insertelement <8 x i16> %ins6, i16 %a3, i32 7714 store <8 x i16> %ins7, ptr %dst715 ret void716}717 718define void @buildvector_v8i16_subseq_4(ptr %dst, i16 %a0, i16 %a1) nounwind {719; CHECK-LABEL: buildvector_v8i16_subseq_4:720; CHECK: # %bb.0: # %entry721; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0722; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1723; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0724; CHECK-NEXT: vst $vr0, $a0, 0725; CHECK-NEXT: ret726entry:727 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0728 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1729 %ins2 = insertelement <8 x i16> %ins1, i16 %a0, i32 2730 %ins3 = insertelement <8 x i16> %ins2, i16 %a1, i32 3731 %ins4 = insertelement <8 x i16> %ins3, i16 %a0, i32 4732 %ins5 = insertelement <8 x i16> %ins4, i16 %a1, i32 5733 %ins6 = insertelement <8 x i16> %ins5, i16 %a0, i32 6734 %ins7 = insertelement <8 x i16> %ins6, i16 %a1, i32 7735 store <8 x i16> %ins7, ptr %dst736 ret void737}738 739define void @buildvector_v4i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {740; CHECK-LABEL: buildvector_v4i32:741; CHECK: # %bb.0: # %entry742; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0743; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1744; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 2745; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 3746; CHECK-NEXT: vst $vr0, $a0, 0747; CHECK-NEXT: ret748entry:749 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0750 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1751 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2752 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3753 store <4 x i32> %ins3, ptr %dst754 ret void755}756 757define void @buildvector_v4i32_partial(ptr %dst, i32 %a0, i32 %a3) nounwind {758; CHECK-LABEL: buildvector_v4i32_partial:759; CHECK: # %bb.0: # %entry760; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0761; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 3762; CHECK-NEXT: vst $vr0, $a0, 0763; CHECK-NEXT: ret764entry:765 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0766 %ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1767 %ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2768 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3769 store <4 x i32> %ins3, ptr %dst770 ret void771}772 773define void @buildvector_v4i32_with_constant(ptr %dst, i32 %a0, i32 %a2, i32 %a3) nounwind {774; CHECK-LABEL: buildvector_v4i32_with_constant:775; CHECK: # %bb.0: # %entry776; CHECK-NEXT: vrepli.w $vr0, 2777; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0778; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 2779; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 3780; CHECK-NEXT: vst $vr0, $a0, 0781; CHECK-NEXT: ret782entry:783 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0784 %ins1 = insertelement <4 x i32> %ins0, i32 2, i32 1785 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2786 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3787 store <4 x i32> %ins3, ptr %dst788 ret void789}790 791define void @buildvector_v4i32_subseq_2(ptr %dst, i32 %a0, i32 %a1) nounwind {792; CHECK-LABEL: buildvector_v4i32_subseq_2:793; CHECK: # %bb.0: # %entry794; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0795; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1796; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0797; CHECK-NEXT: vst $vr0, $a0, 0798; CHECK-NEXT: ret799entry:800 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0801 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1802 %ins2 = insertelement <4 x i32> %ins1, i32 %a0, i32 2803 %ins3 = insertelement <4 x i32> %ins2, i32 %a1, i32 3804 store <4 x i32> %ins3, ptr %dst805 ret void806}807 808define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind {809; LA32-LABEL: buildvector_v2i64:810; LA32: # %bb.0: # %entry811; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0812; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1813; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 2814; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 3815; LA32-NEXT: vst $vr0, $a0, 0816; LA32-NEXT: ret817;818; LA64-LABEL: buildvector_v2i64:819; LA64: # %bb.0: # %entry820; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0821; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 1822; LA64-NEXT: vst $vr0, $a0, 0823; LA64-NEXT: ret824entry:825 %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0826 %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1827 store <2 x i64> %ins1, ptr %dst828 ret void829}830 831define void @buildvector_v2i64_partial(ptr %dst, i64 %a0) nounwind {832; LA32-LABEL: buildvector_v2i64_partial:833; LA32: # %bb.0: # %entry834; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0835; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1836; LA32-NEXT: vst $vr0, $a0, 0837; LA32-NEXT: ret838;839; LA64-LABEL: buildvector_v2i64_partial:840; LA64: # %bb.0: # %entry841; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0842; LA64-NEXT: vst $vr0, $a0, 0843; LA64-NEXT: ret844entry:845 %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0846 %ins1 = insertelement <2 x i64> %ins0, i64 undef, i32 1847 store <2 x i64> %ins1, ptr %dst848 ret void849}850 851define void @buildvector_v2i64_with_constant(ptr %dst, i64 %a1) nounwind {852; LA32-LABEL: buildvector_v2i64_with_constant:853; LA32: # %bb.0: # %entry854; LA32-NEXT: vrepli.b $vr0, 0855; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2856; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3857; LA32-NEXT: vst $vr0, $a0, 0858; LA32-NEXT: ret859;860; LA64-LABEL: buildvector_v2i64_with_constant:861; LA64: # %bb.0: # %entry862; LA64-NEXT: vrepli.b $vr0, 0863; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1864; LA64-NEXT: vst $vr0, $a0, 0865; LA64-NEXT: ret866entry:867 %ins0 = insertelement <2 x i64> undef, i64 0, i32 0868 %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1869 store <2 x i64> %ins1, ptr %dst870 ret void871}872 873define void @buildvector_v4f32(ptr %dst, float %a0, float %a1, float %a2, float %a3) nounwind {874; CHECK-LABEL: buildvector_v4f32:875; CHECK: # %bb.0: # %entry876; CHECK-NEXT: # kill: def $f3 killed $f3 def $vr3877; CHECK-NEXT: # kill: def $f2 killed $f2 def $vr2878; CHECK-NEXT: # kill: def $f1 killed $f1 def $vr1879; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0880; CHECK-NEXT: vextrins.w $vr0, $vr1, 16881; CHECK-NEXT: vextrins.w $vr0, $vr2, 32882; CHECK-NEXT: vextrins.w $vr0, $vr3, 48883; CHECK-NEXT: vst $vr0, $a0, 0884; CHECK-NEXT: ret885entry:886 %ins0 = insertelement <4 x float> undef, float %a0, i32 0887 %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1888 %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2889 %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3890 store <4 x float> %ins3, ptr %dst891 ret void892}893 894define void @buildvector_v4f32_partial(ptr %dst, float %a0, float %a3) nounwind {895; CHECK-LABEL: buildvector_v4f32_partial:896; CHECK: # %bb.0: # %entry897; CHECK-NEXT: # kill: def $f1 killed $f1 def $vr1898; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0899; CHECK-NEXT: vextrins.w $vr0, $vr1, 48900; CHECK-NEXT: vst $vr0, $a0, 0901; CHECK-NEXT: ret902entry:903 %ins0 = insertelement <4 x float> undef, float %a0, i32 0904 %ins1 = insertelement <4 x float> %ins0, float undef, i32 1905 %ins2 = insertelement <4 x float> %ins1, float undef, i32 2906 %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3907 store <4 x float> %ins3, ptr %dst908 ret void909}910 911define void @buildvector_v4f32_with_constant(ptr %dst, float %a1, float %a2, float %a3) nounwind {912; CHECK-LABEL: buildvector_v4f32_with_constant:913; CHECK: # %bb.0: # %entry914; CHECK-NEXT: # kill: def $f2 killed $f2 def $vr2915; CHECK-NEXT: # kill: def $f1 killed $f1 def $vr1916; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0917; CHECK-NEXT: vrepli.b $vr3, 0918; CHECK-NEXT: vextrins.w $vr3, $vr0, 16919; CHECK-NEXT: vextrins.w $vr3, $vr1, 32920; CHECK-NEXT: vextrins.w $vr3, $vr2, 48921; CHECK-NEXT: vst $vr3, $a0, 0922; CHECK-NEXT: ret923entry:924 %ins0 = insertelement <4 x float> undef, float 0.0, i32 0925 %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1926 %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2927 %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3928 store <4 x float> %ins3, ptr %dst929 ret void930}931 932define void @buildvector_v4f32_subseq_2(ptr %dst, float %a0, float %a1) nounwind {933; CHECK-LABEL: buildvector_v4f32_subseq_2:934; CHECK: # %bb.0: # %entry935; CHECK-NEXT: # kill: def $f1 killed $f1 def $vr1936; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0937; CHECK-NEXT: vextrins.w $vr0, $vr1, 16938; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0939; CHECK-NEXT: vst $vr0, $a0, 0940; CHECK-NEXT: ret941entry:942 %ins0 = insertelement <4 x float> undef, float %a0, i32 0943 %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1944 %ins2 = insertelement <4 x float> %ins1, float %a0, i32 2945 %ins3 = insertelement <4 x float> %ins2, float %a1, i32 3946 store <4 x float> %ins3, ptr %dst947 ret void948}949 950define void @buildvector_v2f64(ptr %dst, double %a0, double %a1) nounwind {951; CHECK-LABEL: buildvector_v2f64:952; CHECK: # %bb.0: # %entry953; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 def $vr1954; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0955; CHECK-NEXT: vextrins.d $vr0, $vr1, 16956; CHECK-NEXT: vst $vr0, $a0, 0957; CHECK-NEXT: ret958entry:959 %ins0 = insertelement <2 x double> undef, double %a0, i32 0960 %ins1 = insertelement <2 x double> %ins0, double %a1, i32 1961 store <2 x double> %ins1, ptr %dst962 ret void963}964 965define void @buildvector_v2f64_partial(ptr %dst, double %a1) nounwind {966; CHECK-LABEL: buildvector_v2f64_partial:967; CHECK: # %bb.0: # %entry968; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0969; CHECK-NEXT: vextrins.d $vr0, $vr0, 16970; CHECK-NEXT: vst $vr0, $a0, 0971; CHECK-NEXT: ret972entry:973 %ins0 = insertelement <2 x double> undef, double undef, i32 0974 %ins1 = insertelement <2 x double> %ins0, double %a1, i32 1975 store <2 x double> %ins1, ptr %dst976 ret void977}978 979define void @buildvector_v2f64_with_constant(ptr %dst, double %a0) nounwind {980; CHECK-LABEL: buildvector_v2f64_with_constant:981; CHECK: # %bb.0: # %entry982; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0983; CHECK-NEXT: vldi $vr1, -1024984; CHECK-NEXT: vpackev.d $vr0, $vr1, $vr0985; CHECK-NEXT: vst $vr0, $a0, 0986; CHECK-NEXT: ret987entry:988 %ins0 = insertelement <2 x double> undef, double %a0, i32 0989 %ins1 = insertelement <2 x double> %ins0, double 2.0, i32 1990 store <2 x double> %ins1, ptr %dst991 ret void992}993 994;; If `isShuffleMaskLegal` returns true, it will lead to an infinite loop.995define void @extract1_i32_zext_insert0_i64_undef(ptr %src, ptr %dst) nounwind {996; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef:997; CHECK: # %bb.0:998; CHECK-NEXT: vld $vr0, $a0, 0999; CHECK-NEXT: vsrli.d $vr0, $vr0, 321000; CHECK-NEXT: vst $vr0, $a1, 01001; CHECK-NEXT: ret1002 %v = load volatile <4 x i32>, ptr %src1003 %e = extractelement <4 x i32> %v, i32 11004 %z = zext i32 %e to i641005 %r = insertelement <2 x i64> undef, i64 %z, i32 01006 store <2 x i64> %r, ptr %dst1007 ret void1008}1009