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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s4 5define void @ctpop_v16i8(ptr %src, ptr %dst) nounwind {6; CHECK-LABEL: ctpop_v16i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vld $vr0, $a0, 09; CHECK-NEXT: vpcnt.b $vr0, $vr010; CHECK-NEXT: vst $vr0, $a1, 011; CHECK-NEXT: ret12 %v = load <16 x i8>, ptr %src13 %res = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %v)14 store <16 x i8> %res, ptr %dst15 ret void16}17 18define void @ctpop_v8i16(ptr %src, ptr %dst) nounwind {19; CHECK-LABEL: ctpop_v8i16:20; CHECK: # %bb.0:21; CHECK-NEXT: vld $vr0, $a0, 022; CHECK-NEXT: vpcnt.h $vr0, $vr023; CHECK-NEXT: vst $vr0, $a1, 024; CHECK-NEXT: ret25 %v = load <8 x i16>, ptr %src26 %res = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %v)27 store <8 x i16> %res, ptr %dst28 ret void29}30 31define void @ctpop_v4i32(ptr %src, ptr %dst) nounwind {32; CHECK-LABEL: ctpop_v4i32:33; CHECK: # %bb.0:34; CHECK-NEXT: vld $vr0, $a0, 035; CHECK-NEXT: vpcnt.w $vr0, $vr036; CHECK-NEXT: vst $vr0, $a1, 037; CHECK-NEXT: ret38 %v = load <4 x i32>, ptr %src39 %res = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %v)40 store <4 x i32> %res, ptr %dst41 ret void42}43 44define void @ctpop_v2i64(ptr %src, ptr %dst) nounwind {45; CHECK-LABEL: ctpop_v2i64:46; CHECK: # %bb.0:47; CHECK-NEXT: vld $vr0, $a0, 048; CHECK-NEXT: vpcnt.d $vr0, $vr049; CHECK-NEXT: vst $vr0, $a1, 050; CHECK-NEXT: ret51 %v = load <2 x i64>, ptr %src52 %res = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %v)53 store <2 x i64> %res, ptr %dst54 ret void55}56 57define void @ctlz_v16i8(ptr %src, ptr %dst) nounwind {58; CHECK-LABEL: ctlz_v16i8:59; CHECK: # %bb.0:60; CHECK-NEXT: vld $vr0, $a0, 061; CHECK-NEXT: vclz.b $vr0, $vr062; CHECK-NEXT: vst $vr0, $a1, 063; CHECK-NEXT: ret64 %v = load <16 x i8>, ptr %src65 %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %v, i1 false)66 store <16 x i8> %res, ptr %dst67 ret void68}69 70define void @ctlz_v8i16(ptr %src, ptr %dst) nounwind {71; CHECK-LABEL: ctlz_v8i16:72; CHECK: # %bb.0:73; CHECK-NEXT: vld $vr0, $a0, 074; CHECK-NEXT: vclz.h $vr0, $vr075; CHECK-NEXT: vst $vr0, $a1, 076; CHECK-NEXT: ret77 %v = load <8 x i16>, ptr %src78 %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %v, i1 false)79 store <8 x i16> %res, ptr %dst80 ret void81}82 83define void @ctlz_v4i32(ptr %src, ptr %dst) nounwind {84; CHECK-LABEL: ctlz_v4i32:85; CHECK: # %bb.0:86; CHECK-NEXT: vld $vr0, $a0, 087; CHECK-NEXT: vclz.w $vr0, $vr088; CHECK-NEXT: vst $vr0, $a1, 089; CHECK-NEXT: ret90 %v = load <4 x i32>, ptr %src91 %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %v, i1 false)92 store <4 x i32> %res, ptr %dst93 ret void94}95 96define void @ctlz_v2i64(ptr %src, ptr %dst) nounwind {97; CHECK-LABEL: ctlz_v2i64:98; CHECK: # %bb.0:99; CHECK-NEXT: vld $vr0, $a0, 0100; CHECK-NEXT: vclz.d $vr0, $vr0101; CHECK-NEXT: vst $vr0, $a1, 0102; CHECK-NEXT: ret103 %v = load <2 x i64>, ptr %src104 %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %v, i1 false)105 store <2 x i64> %res, ptr %dst106 ret void107}108 109define void @not_ctlz_v16i8(ptr %src, ptr %dst) nounwind {110; CHECK-LABEL: not_ctlz_v16i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vld $vr0, $a0, 0113; CHECK-NEXT: vxori.b $vr0, $vr0, 255114; CHECK-NEXT: vclz.b $vr0, $vr0115; CHECK-NEXT: vst $vr0, $a1, 0116; CHECK-NEXT: ret117 %v = load <16 x i8>, ptr %src118 %neg = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>119 %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %neg, i1 false)120 store <16 x i8> %res, ptr %dst121 ret void122}123 124define void @not_ctlz_v8i16(ptr %src, ptr %dst) nounwind {125; CHECK-LABEL: not_ctlz_v8i16:126; CHECK: # %bb.0:127; CHECK-NEXT: vld $vr0, $a0, 0128; CHECK-NEXT: vrepli.b $vr1, -1129; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1130; CHECK-NEXT: vclz.h $vr0, $vr0131; CHECK-NEXT: vst $vr0, $a1, 0132; CHECK-NEXT: ret133 %v = load <8 x i16>, ptr %src134 %neg = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>135 %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %neg, i1 false)136 store <8 x i16> %res, ptr %dst137 ret void138}139 140define void @not_ctlz_v4i32(ptr %src, ptr %dst) nounwind {141; CHECK-LABEL: not_ctlz_v4i32:142; CHECK: # %bb.0:143; CHECK-NEXT: vld $vr0, $a0, 0144; CHECK-NEXT: vrepli.b $vr1, -1145; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1146; CHECK-NEXT: vclz.w $vr0, $vr0147; CHECK-NEXT: vst $vr0, $a1, 0148; CHECK-NEXT: ret149 %v = load <4 x i32>, ptr %src150 %neg = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>151 %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %neg, i1 false)152 store <4 x i32> %res, ptr %dst153 ret void154}155 156define void @not_ctlz_v2i64(ptr %src, ptr %dst) nounwind {157; CHECK-LABEL: not_ctlz_v2i64:158; CHECK: # %bb.0:159; CHECK-NEXT: vld $vr0, $a0, 0160; CHECK-NEXT: vrepli.b $vr1, -1161; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1162; CHECK-NEXT: vclz.d $vr0, $vr0163; CHECK-NEXT: vst $vr0, $a1, 0164; CHECK-NEXT: ret165 %v = load <2 x i64>, ptr %src166 %neg = xor <2 x i64> %v, <i64 -1, i64 -1>167 %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %neg, i1 false)168 store <2 x i64> %res, ptr %dst169 ret void170}171 172declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)173declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)174declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)175declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)176declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)177declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)178declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)179declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)180