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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define void @register_vr1() nounwind {6; CHECK-LABEL: register_vr1:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: #APP9; CHECK-NEXT: vldi $vr1, 110; CHECK-NEXT: #NO_APP11; CHECK-NEXT: ret12entry:13 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr1}"()14 ret void15}16 17define void @register_vr7() nounwind {18; CHECK-LABEL: register_vr7:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: #APP21; CHECK-NEXT: vldi $vr7, 122; CHECK-NEXT: #NO_APP23; CHECK-NEXT: ret24entry:25 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr7}"()26 ret void27}28 29define void @register_vr23() nounwind {30; CHECK-LABEL: register_vr23:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: #APP33; CHECK-NEXT: vldi $vr23, 134; CHECK-NEXT: #NO_APP35; CHECK-NEXT: ret36entry:37 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr23}"()38 ret void39}40 41;; The lower half of the vector register '$vr31' is overlapped with42;; the floating-point register '$f31'. And '$f31' is a callee-saved43;; register which is preserved across calls. That's why the44;; fst.d and fld.d instructions are emitted.45define void @register_vr31() nounwind {46; LA32-LABEL: register_vr31:47; LA32: # %bb.0: # %entry48; LA32-NEXT: addi.w $sp, $sp, -1649; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill50; LA32-NEXT: #APP51; LA32-NEXT: vldi $vr31, 152; LA32-NEXT: #NO_APP53; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload54; LA32-NEXT: addi.w $sp, $sp, 1655; LA32-NEXT: ret56;57; LA64-LABEL: register_vr31:58; LA64: # %bb.0: # %entry59; LA64-NEXT: addi.d $sp, $sp, -1660; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill61; LA64-NEXT: #APP62; LA64-NEXT: vldi $vr31, 163; LA64-NEXT: #NO_APP64; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload65; LA64-NEXT: addi.d $sp, $sp, 1666; LA64-NEXT: ret67entry:68 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr31}"()69 ret void70}71