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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5declare <16 x i8> @llvm.loongarch.lsx.vbitrev.b(<16 x i8>, <16 x i8>)6 7define <16 x i8> @lsx_vbitrev_b(<16 x i8> %va, <16 x i8> %vb) nounwind {8; CHECK-LABEL: lsx_vbitrev_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vbitrev.b $vr0, $vr0, $vr111; CHECK-NEXT: ret12entry:13 %res = call <16 x i8> @llvm.loongarch.lsx.vbitrev.b(<16 x i8> %va, <16 x i8> %vb)14 ret <16 x i8> %res15}16 17declare <8 x i16> @llvm.loongarch.lsx.vbitrev.h(<8 x i16>, <8 x i16>)18 19define <8 x i16> @lsx_vbitrev_h(<8 x i16> %va, <8 x i16> %vb) nounwind {20; CHECK-LABEL: lsx_vbitrev_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vbitrev.h $vr0, $vr0, $vr123; CHECK-NEXT: ret24entry:25 %res = call <8 x i16> @llvm.loongarch.lsx.vbitrev.h(<8 x i16> %va, <8 x i16> %vb)26 ret <8 x i16> %res27}28 29declare <4 x i32> @llvm.loongarch.lsx.vbitrev.w(<4 x i32>, <4 x i32>)30 31define <4 x i32> @lsx_vbitrev_w(<4 x i32> %va, <4 x i32> %vb) nounwind {32; CHECK-LABEL: lsx_vbitrev_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vbitrev.w $vr0, $vr0, $vr135; CHECK-NEXT: ret36entry:37 %res = call <4 x i32> @llvm.loongarch.lsx.vbitrev.w(<4 x i32> %va, <4 x i32> %vb)38 ret <4 x i32> %res39}40 41declare <2 x i64> @llvm.loongarch.lsx.vbitrev.d(<2 x i64>, <2 x i64>)42 43define <2 x i64> @lsx_vbitrev_d(<2 x i64> %va, <2 x i64> %vb) nounwind {44; LA32-LABEL: lsx_vbitrev_d:45; LA32: # %bb.0: # %entry46; LA32-NEXT: vrepli.d $vr2, 6347; LA32-NEXT: vand.v $vr1, $vr1, $vr248; LA32-NEXT: vrepli.d $vr2, 149; LA32-NEXT: vsll.d $vr1, $vr2, $vr150; LA32-NEXT: vxor.v $vr0, $vr0, $vr151; LA32-NEXT: ret52;53; LA64-LABEL: lsx_vbitrev_d:54; LA64: # %bb.0: # %entry55; LA64-NEXT: vbitrev.d $vr0, $vr0, $vr156; LA64-NEXT: ret57entry:58 %res = call <2 x i64> @llvm.loongarch.lsx.vbitrev.d(<2 x i64> %va, <2 x i64> %vb)59 ret <2 x i64> %res60}61 62declare <16 x i8> @llvm.loongarch.lsx.vbitrevi.b(<16 x i8>, i32)63 64define <16 x i8> @lsx_vbitrevi_b(<16 x i8> %va) nounwind {65; CHECK-LABEL: lsx_vbitrevi_b:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: vbitrevi.b $vr0, $vr0, 768; CHECK-NEXT: ret69entry:70 %res = call <16 x i8> @llvm.loongarch.lsx.vbitrevi.b(<16 x i8> %va, i32 7)71 ret <16 x i8> %res72}73 74declare <8 x i16> @llvm.loongarch.lsx.vbitrevi.h(<8 x i16>, i32)75 76define <8 x i16> @lsx_vbitrevi_h(<8 x i16> %va) nounwind {77; CHECK-LABEL: lsx_vbitrevi_h:78; CHECK: # %bb.0: # %entry79; CHECK-NEXT: vbitrevi.h $vr0, $vr0, 1580; CHECK-NEXT: ret81entry:82 %res = call <8 x i16> @llvm.loongarch.lsx.vbitrevi.h(<8 x i16> %va, i32 15)83 ret <8 x i16> %res84}85 86declare <4 x i32> @llvm.loongarch.lsx.vbitrevi.w(<4 x i32>, i32)87 88define <4 x i32> @lsx_vbitrevi_w(<4 x i32> %va) nounwind {89; CHECK-LABEL: lsx_vbitrevi_w:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: vbitrevi.w $vr0, $vr0, 3192; CHECK-NEXT: ret93entry:94 %res = call <4 x i32> @llvm.loongarch.lsx.vbitrevi.w(<4 x i32> %va, i32 31)95 ret <4 x i32> %res96}97 98declare <2 x i64> @llvm.loongarch.lsx.vbitrevi.d(<2 x i64>, i32)99 100define <2 x i64> @lsx_vbitrevi_d(<2 x i64> %va) nounwind {101; LA32-LABEL: lsx_vbitrevi_d:102; LA32: # %bb.0: # %entry103; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)104; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)105; LA32-NEXT: vxor.v $vr0, $vr0, $vr1106; LA32-NEXT: ret107;108; LA64-LABEL: lsx_vbitrevi_d:109; LA64: # %bb.0: # %entry110; LA64-NEXT: vbitrevi.d $vr0, $vr0, 63111; LA64-NEXT: ret112entry:113 %res = call <2 x i64> @llvm.loongarch.lsx.vbitrevi.d(<2 x i64> %va, i32 63)114 ret <2 x i64> %res115}116