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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5declare <8 x i16> @llvm.loongarch.lsx.vexth.h.b(<16 x i8>)6 7define <8 x i16> @lsx_vexth_h_b(<16 x i8> %va) nounwind {8; CHECK-LABEL: lsx_vexth_h_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vexth.h.b $vr0, $vr011; CHECK-NEXT: ret12entry:13 %res = call <8 x i16> @llvm.loongarch.lsx.vexth.h.b(<16 x i8> %va)14 ret <8 x i16> %res15}16 17declare <4 x i32> @llvm.loongarch.lsx.vexth.w.h(<8 x i16>)18 19define <4 x i32> @lsx_vexth_w_h(<8 x i16> %va) nounwind {20; CHECK-LABEL: lsx_vexth_w_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vexth.w.h $vr0, $vr023; CHECK-NEXT: ret24entry:25 %res = call <4 x i32> @llvm.loongarch.lsx.vexth.w.h(<8 x i16> %va)26 ret <4 x i32> %res27}28 29declare <2 x i64> @llvm.loongarch.lsx.vexth.d.w(<4 x i32>)30 31define <2 x i64> @lsx_vexth_d_w(<4 x i32> %va) nounwind {32; CHECK-LABEL: lsx_vexth_d_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vexth.d.w $vr0, $vr035; CHECK-NEXT: ret36entry:37 %res = call <2 x i64> @llvm.loongarch.lsx.vexth.d.w(<4 x i32> %va)38 ret <2 x i64> %res39}40 41declare <2 x i64> @llvm.loongarch.lsx.vexth.q.d(<2 x i64>)42 43define <2 x i64> @lsx_vexth_q_d(<2 x i64> %va) nounwind {44; CHECK-LABEL: lsx_vexth_q_d:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vexth.q.d $vr0, $vr047; CHECK-NEXT: ret48entry:49 %res = call <2 x i64> @llvm.loongarch.lsx.vexth.q.d(<2 x i64> %va)50 ret <2 x i64> %res51}52 53declare <8 x i16> @llvm.loongarch.lsx.vexth.hu.bu(<16 x i8>)54 55define <8 x i16> @lsx_vexth_hu_bu(<16 x i8> %va) nounwind {56; CHECK-LABEL: lsx_vexth_hu_bu:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vexth.hu.bu $vr0, $vr059; CHECK-NEXT: ret60entry:61 %res = call <8 x i16> @llvm.loongarch.lsx.vexth.hu.bu(<16 x i8> %va)62 ret <8 x i16> %res63}64 65declare <4 x i32> @llvm.loongarch.lsx.vexth.wu.hu(<8 x i16>)66 67define <4 x i32> @lsx_vexth_wu_hu(<8 x i16> %va) nounwind {68; CHECK-LABEL: lsx_vexth_wu_hu:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vexth.wu.hu $vr0, $vr071; CHECK-NEXT: ret72entry:73 %res = call <4 x i32> @llvm.loongarch.lsx.vexth.wu.hu(<8 x i16> %va)74 ret <4 x i32> %res75}76 77declare <2 x i64> @llvm.loongarch.lsx.vexth.du.wu(<4 x i32>)78 79define <2 x i64> @lsx_vexth_du_wu(<4 x i32> %va) nounwind {80; CHECK-LABEL: lsx_vexth_du_wu:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vexth.du.wu $vr0, $vr083; CHECK-NEXT: ret84entry:85 %res = call <2 x i64> @llvm.loongarch.lsx.vexth.du.wu(<4 x i32> %va)86 ret <2 x i64> %res87}88 89declare <2 x i64> @llvm.loongarch.lsx.vexth.qu.du(<2 x i64>)90 91define <2 x i64> @lsx_vexth_qu_du(<2 x i64> %va) nounwind {92; CHECK-LABEL: lsx_vexth_qu_du:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: vexth.qu.du $vr0, $vr095; CHECK-NEXT: ret96entry:97 %res = call <2 x i64> @llvm.loongarch.lsx.vexth.qu.du(<2 x i64> %va)98 ret <2 x i64> %res99}100