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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5declare <2 x i64> @llvm.loongarch.lsx.vextl.q.d(<2 x i64>)6 7define <2 x i64> @lsx_vextl_q_d(<2 x i64> %va) nounwind {8; CHECK-LABEL: lsx_vextl_q_d:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vextl.q.d $vr0, $vr011; CHECK-NEXT: ret12entry:13 %res = call <2 x i64> @llvm.loongarch.lsx.vextl.q.d(<2 x i64> %va)14 ret <2 x i64> %res15}16 17declare <2 x i64> @llvm.loongarch.lsx.vextl.qu.du(<2 x i64>)18 19define <2 x i64> @lsx_vextl_qu_du(<2 x i64> %va) nounwind {20; CHECK-LABEL: lsx_vextl_qu_du:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vextl.qu.du $vr0, $vr023; CHECK-NEXT: ret24entry:25 %res = call <2 x i64> @llvm.loongarch.lsx.vextl.qu.du(<2 x i64> %va)26 ret <2 x i64> %res27}28