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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32)6 7define <16 x i8> @lsx_vinsgr2vr_b(<16 x i8> %va) nounwind {8; CHECK-LABEL: lsx_vinsgr2vr_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: ori $a0, $zero, 111; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 1512; CHECK-NEXT: ret13entry:14 %res = call <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8> %va, i32 1, i32 15)15 ret <16 x i8> %res16}17 18declare <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16>, i32, i32)19 20define <8 x i16> @lsx_vinsgr2vr_h(<8 x i16> %va) nounwind {21; CHECK-LABEL: lsx_vinsgr2vr_h:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: ori $a0, $zero, 124; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 725; CHECK-NEXT: ret26entry:27 %res = call <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16> %va, i32 1, i32 7)28 ret <8 x i16> %res29}30 31declare <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32>, i32, i32)32 33define <4 x i32> @lsx_vinsgr2vr_w(<4 x i32> %va) nounwind {34; CHECK-LABEL: lsx_vinsgr2vr_w:35; CHECK: # %bb.0: # %entry36; CHECK-NEXT: ori $a0, $zero, 137; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 338; CHECK-NEXT: ret39entry:40 %res = call <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32> %va, i32 1, i32 3)41 ret <4 x i32> %res42}43 44declare <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64>, i64, i32)45 46define <2 x i64> @lsx_vinsgr2vr_d(<2 x i64> %va) nounwind {47; LA32-LABEL: lsx_vinsgr2vr_d:48; LA32: # %bb.0: # %entry49; LA32-NEXT: ori $a0, $zero, 150; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 251; LA32-NEXT: vinsgr2vr.w $vr0, $zero, 352; LA32-NEXT: ret53;54; LA64-LABEL: lsx_vinsgr2vr_d:55; LA64: # %bb.0: # %entry56; LA64-NEXT: ori $a0, $zero, 157; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 158; LA64-NEXT: ret59entry:60 %res = call <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64> %va, i64 1, i32 1)61 ret <2 x i64> %res62}63