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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)6 7define <8 x i16> @lsx_vsllwil_h_b(<16 x i8> %va) nounwind {8; CHECK-LABEL: lsx_vsllwil_h_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsllwil.h.b $vr0, $vr0, 111; CHECK-NEXT: ret12entry:13 %res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8> %va, i32 1)14 ret <8 x i16> %res15}16 17declare <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16>, i32)18 19define <4 x i32> @lsx_vsllwil_w_h(<8 x i16> %va) nounwind {20; CHECK-LABEL: lsx_vsllwil_w_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vsllwil.w.h $vr0, $vr0, 123; CHECK-NEXT: ret24entry:25 %res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16> %va, i32 1)26 ret <4 x i32> %res27}28 29declare <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32>, i32)30 31define <2 x i64> @lsx_vsllwil_d_w(<4 x i32> %va) nounwind {32; CHECK-LABEL: lsx_vsllwil_d_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vsllwil.d.w $vr0, $vr0, 135; CHECK-NEXT: ret36entry:37 %res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32> %va, i32 1)38 ret <2 x i64> %res39}40 41declare <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8>, i32)42 43define <8 x i16> @lsx_vsllwil_hu_bu(<16 x i8> %va) nounwind {44; CHECK-LABEL: lsx_vsllwil_hu_bu:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vsllwil.hu.bu $vr0, $vr0, 747; CHECK-NEXT: ret48entry:49 %res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8> %va, i32 7)50 ret <8 x i16> %res51}52 53declare <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16>, i32)54 55define <4 x i32> @lsx_vsllwil_wu_hu(<8 x i16> %va) nounwind {56; CHECK-LABEL: lsx_vsllwil_wu_hu:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsllwil.wu.hu $vr0, $vr0, 1559; CHECK-NEXT: ret60entry:61 %res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16> %va, i32 15)62 ret <4 x i32> %res63}64 65declare <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32>, i32)66 67define <2 x i64> @lsx_vsllwil_du_wu(<4 x i32> %va) nounwind {68; CHECK-LABEL: lsx_vsllwil_du_wu:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsllwil.du.wu $vr0, $vr0, 3171; CHECK-NEXT: ret72entry:73 %res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32> %va, i32 31)74 ret <2 x i64> %res75}76