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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5declare <16 x i8> @llvm.loongarch.lsx.vslt.b(<16 x i8>, <16 x i8>)6 7define <16 x i8> @lsx_vslt_b(<16 x i8> %va, <16 x i8> %vb) nounwind {8; CHECK-LABEL: lsx_vslt_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vslt.b $vr0, $vr0, $vr111; CHECK-NEXT: ret12entry:13 %res = call <16 x i8> @llvm.loongarch.lsx.vslt.b(<16 x i8> %va, <16 x i8> %vb)14 ret <16 x i8> %res15}16 17declare <8 x i16> @llvm.loongarch.lsx.vslt.h(<8 x i16>, <8 x i16>)18 19define <8 x i16> @lsx_vslt_h(<8 x i16> %va, <8 x i16> %vb) nounwind {20; CHECK-LABEL: lsx_vslt_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vslt.h $vr0, $vr0, $vr123; CHECK-NEXT: ret24entry:25 %res = call <8 x i16> @llvm.loongarch.lsx.vslt.h(<8 x i16> %va, <8 x i16> %vb)26 ret <8 x i16> %res27}28 29declare <4 x i32> @llvm.loongarch.lsx.vslt.w(<4 x i32>, <4 x i32>)30 31define <4 x i32> @lsx_vslt_w(<4 x i32> %va, <4 x i32> %vb) nounwind {32; CHECK-LABEL: lsx_vslt_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vslt.w $vr0, $vr0, $vr135; CHECK-NEXT: ret36entry:37 %res = call <4 x i32> @llvm.loongarch.lsx.vslt.w(<4 x i32> %va, <4 x i32> %vb)38 ret <4 x i32> %res39}40 41declare <2 x i64> @llvm.loongarch.lsx.vslt.d(<2 x i64>, <2 x i64>)42 43define <2 x i64> @lsx_vslt_d(<2 x i64> %va, <2 x i64> %vb) nounwind {44; CHECK-LABEL: lsx_vslt_d:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vslt.d $vr0, $vr0, $vr147; CHECK-NEXT: ret48entry:49 %res = call <2 x i64> @llvm.loongarch.lsx.vslt.d(<2 x i64> %va, <2 x i64> %vb)50 ret <2 x i64> %res51}52 53declare <16 x i8> @llvm.loongarch.lsx.vslti.b(<16 x i8>, i32)54 55define <16 x i8> @lsx_vslti_b(<16 x i8> %va) nounwind {56; CHECK-LABEL: lsx_vslti_b:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vslti.b $vr0, $vr0, 1559; CHECK-NEXT: ret60entry:61 %res = call <16 x i8> @llvm.loongarch.lsx.vslti.b(<16 x i8> %va, i32 15)62 ret <16 x i8> %res63}64 65declare <8 x i16> @llvm.loongarch.lsx.vslti.h(<8 x i16>, i32)66 67define <8 x i16> @lsx_vslti_h(<8 x i16> %va) nounwind {68; CHECK-LABEL: lsx_vslti_h:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vslti.h $vr0, $vr0, 1571; CHECK-NEXT: ret72entry:73 %res = call <8 x i16> @llvm.loongarch.lsx.vslti.h(<8 x i16> %va, i32 15)74 ret <8 x i16> %res75}76 77declare <4 x i32> @llvm.loongarch.lsx.vslti.w(<4 x i32>, i32)78 79define <4 x i32> @lsx_vslti_w(<4 x i32> %va) nounwind {80; CHECK-LABEL: lsx_vslti_w:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vslti.w $vr0, $vr0, -1683; CHECK-NEXT: ret84entry:85 %res = call <4 x i32> @llvm.loongarch.lsx.vslti.w(<4 x i32> %va, i32 -16)86 ret <4 x i32> %res87}88 89declare <2 x i64> @llvm.loongarch.lsx.vslti.d(<2 x i64>, i32)90 91define <2 x i64> @lsx_vslti_d(<2 x i64> %va) nounwind {92; CHECK-LABEL: lsx_vslti_d:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: vslti.d $vr0, $vr0, -1695; CHECK-NEXT: ret96entry:97 %res = call <2 x i64> @llvm.loongarch.lsx.vslti.d(<2 x i64> %va, i32 -16)98 ret <2 x i64> %res99}100 101declare <16 x i8> @llvm.loongarch.lsx.vslt.bu(<16 x i8>, <16 x i8>)102 103define <16 x i8> @lsx_vslt_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {104; CHECK-LABEL: lsx_vslt_bu:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vslt.bu $vr0, $vr0, $vr1107; CHECK-NEXT: ret108entry:109 %res = call <16 x i8> @llvm.loongarch.lsx.vslt.bu(<16 x i8> %va, <16 x i8> %vb)110 ret <16 x i8> %res111}112 113declare <8 x i16> @llvm.loongarch.lsx.vslt.hu(<8 x i16>, <8 x i16>)114 115define <8 x i16> @lsx_vslt_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {116; CHECK-LABEL: lsx_vslt_hu:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vslt.hu $vr0, $vr0, $vr1119; CHECK-NEXT: ret120entry:121 %res = call <8 x i16> @llvm.loongarch.lsx.vslt.hu(<8 x i16> %va, <8 x i16> %vb)122 ret <8 x i16> %res123}124 125declare <4 x i32> @llvm.loongarch.lsx.vslt.wu(<4 x i32>, <4 x i32>)126 127define <4 x i32> @lsx_vslt_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {128; CHECK-LABEL: lsx_vslt_wu:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vslt.wu $vr0, $vr0, $vr1131; CHECK-NEXT: ret132entry:133 %res = call <4 x i32> @llvm.loongarch.lsx.vslt.wu(<4 x i32> %va, <4 x i32> %vb)134 ret <4 x i32> %res135}136 137declare <2 x i64> @llvm.loongarch.lsx.vslt.du(<2 x i64>, <2 x i64>)138 139define <2 x i64> @lsx_vslt_du(<2 x i64> %va, <2 x i64> %vb) nounwind {140; CHECK-LABEL: lsx_vslt_du:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vslt.du $vr0, $vr0, $vr1143; CHECK-NEXT: ret144entry:145 %res = call <2 x i64> @llvm.loongarch.lsx.vslt.du(<2 x i64> %va, <2 x i64> %vb)146 ret <2 x i64> %res147}148 149declare <16 x i8> @llvm.loongarch.lsx.vslti.bu(<16 x i8>, i32)150 151define <16 x i8> @lsx_vslti_bu(<16 x i8> %va) nounwind {152; CHECK-LABEL: lsx_vslti_bu:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vslti.bu $vr0, $vr0, 1155; CHECK-NEXT: ret156entry:157 %res = call <16 x i8> @llvm.loongarch.lsx.vslti.bu(<16 x i8> %va, i32 1)158 ret <16 x i8> %res159}160 161declare <8 x i16> @llvm.loongarch.lsx.vslti.hu(<8 x i16>, i32)162 163define <8 x i16> @lsx_vslti_hu(<8 x i16> %va) nounwind {164; CHECK-LABEL: lsx_vslti_hu:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: vslti.hu $vr0, $vr0, 1167; CHECK-NEXT: ret168entry:169 %res = call <8 x i16> @llvm.loongarch.lsx.vslti.hu(<8 x i16> %va, i32 1)170 ret <8 x i16> %res171}172 173declare <4 x i32> @llvm.loongarch.lsx.vslti.wu(<4 x i32>, i32)174 175define <4 x i32> @lsx_vslti_wu(<4 x i32> %va) nounwind {176; CHECK-LABEL: lsx_vslti_wu:177; CHECK: # %bb.0: # %entry178; CHECK-NEXT: vslti.wu $vr0, $vr0, 31179; CHECK-NEXT: ret180entry:181 %res = call <4 x i32> @llvm.loongarch.lsx.vslti.wu(<4 x i32> %va, i32 31)182 ret <4 x i32> %res183}184 185declare <2 x i64> @llvm.loongarch.lsx.vslti.du(<2 x i64>, i32)186 187define <2 x i64> @lsx_vslti_du(<2 x i64> %va) nounwind {188; CHECK-LABEL: lsx_vslti_du:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: vslti.du $vr0, $vr0, 31191; CHECK-NEXT: ret192entry:193 %res = call <2 x i64> @llvm.loongarch.lsx.vslti.du(<2 x i64> %va, i32 31)194 ret <2 x i64> %res195}196