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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5declare <16 x i8> @llvm.loongarch.lsx.vsra.b(<16 x i8>, <16 x i8>)6 7define <16 x i8> @lsx_vsra_b(<16 x i8> %va, <16 x i8> %vb) nounwind {8; CHECK-LABEL: lsx_vsra_b:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsra.b $vr0, $vr0, $vr111; CHECK-NEXT: ret12entry:13 %res = call <16 x i8> @llvm.loongarch.lsx.vsra.b(<16 x i8> %va, <16 x i8> %vb)14 ret <16 x i8> %res15}16 17declare <8 x i16> @llvm.loongarch.lsx.vsra.h(<8 x i16>, <8 x i16>)18 19define <8 x i16> @lsx_vsra_h(<8 x i16> %va, <8 x i16> %vb) nounwind {20; CHECK-LABEL: lsx_vsra_h:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vsra.h $vr0, $vr0, $vr123; CHECK-NEXT: ret24entry:25 %res = call <8 x i16> @llvm.loongarch.lsx.vsra.h(<8 x i16> %va, <8 x i16> %vb)26 ret <8 x i16> %res27}28 29declare <4 x i32> @llvm.loongarch.lsx.vsra.w(<4 x i32>, <4 x i32>)30 31define <4 x i32> @lsx_vsra_w(<4 x i32> %va, <4 x i32> %vb) nounwind {32; CHECK-LABEL: lsx_vsra_w:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vsra.w $vr0, $vr0, $vr135; CHECK-NEXT: ret36entry:37 %res = call <4 x i32> @llvm.loongarch.lsx.vsra.w(<4 x i32> %va, <4 x i32> %vb)38 ret <4 x i32> %res39}40 41declare <2 x i64> @llvm.loongarch.lsx.vsra.d(<2 x i64>, <2 x i64>)42 43define <2 x i64> @lsx_vsra_d(<2 x i64> %va, <2 x i64> %vb) nounwind {44; LA32-LABEL: lsx_vsra_d:45; LA32: # %bb.0: # %entry46; LA32-NEXT: vrepli.d $vr2, 6347; LA32-NEXT: vand.v $vr1, $vr1, $vr248; LA32-NEXT: vsra.d $vr0, $vr0, $vr149; LA32-NEXT: ret50;51; LA64-LABEL: lsx_vsra_d:52; LA64: # %bb.0: # %entry53; LA64-NEXT: vsra.d $vr0, $vr0, $vr154; LA64-NEXT: ret55entry:56 %res = call <2 x i64> @llvm.loongarch.lsx.vsra.d(<2 x i64> %va, <2 x i64> %vb)57 ret <2 x i64> %res58}59 60declare <16 x i8> @llvm.loongarch.lsx.vsrai.b(<16 x i8>, i32)61 62define <16 x i8> @lsx_vsrai_b(<16 x i8> %va) nounwind {63; CHECK-LABEL: lsx_vsrai_b:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsrai.b $vr0, $vr0, 766; CHECK-NEXT: ret67entry:68 %res = call <16 x i8> @llvm.loongarch.lsx.vsrai.b(<16 x i8> %va, i32 7)69 ret <16 x i8> %res70}71 72declare <8 x i16> @llvm.loongarch.lsx.vsrai.h(<8 x i16>, i32)73 74define <8 x i16> @lsx_vsrai_h(<8 x i16> %va) nounwind {75; CHECK-LABEL: lsx_vsrai_h:76; CHECK: # %bb.0: # %entry77; CHECK-NEXT: vsrai.h $vr0, $vr0, 1578; CHECK-NEXT: ret79entry:80 %res = call <8 x i16> @llvm.loongarch.lsx.vsrai.h(<8 x i16> %va, i32 15)81 ret <8 x i16> %res82}83 84declare <4 x i32> @llvm.loongarch.lsx.vsrai.w(<4 x i32>, i32)85 86define <4 x i32> @lsx_vsrai_w(<4 x i32> %va) nounwind {87; CHECK-LABEL: lsx_vsrai_w:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: vsrai.w $vr0, $vr0, 3190; CHECK-NEXT: ret91entry:92 %res = call <4 x i32> @llvm.loongarch.lsx.vsrai.w(<4 x i32> %va, i32 31)93 ret <4 x i32> %res94}95 96declare <2 x i64> @llvm.loongarch.lsx.vsrai.d(<2 x i64>, i32)97 98define <2 x i64> @lsx_vsrai_d(<2 x i64> %va) nounwind {99; CHECK-LABEL: lsx_vsrai_d:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsrai.d $vr0, $vr0, 63102; CHECK-NEXT: ret103entry:104 %res = call <2 x i64> @llvm.loongarch.lsx.vsrai.d(<2 x i64> %va, i32 63)105 ret <2 x i64> %res106}107