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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32)6 7define <16 x i8> @lsx_vsrani_b_h(<16 x i8> %va, <16 x i8> %vb) nounwind {8; CHECK-LABEL: lsx_vsrani_b_h:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsrani.b.h $vr0, $vr1, 1511; CHECK-NEXT: ret12entry:13 %res = call <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8> %va, <16 x i8> %vb, i32 15)14 ret <16 x i8> %res15}16 17declare <8 x i16> @llvm.loongarch.lsx.vsrani.h.w(<8 x i16>, <8 x i16>, i32)18 19define <8 x i16> @lsx_vsrani_h_w(<8 x i16> %va, <8 x i16> %vb) nounwind {20; CHECK-LABEL: lsx_vsrani_h_w:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vsrani.h.w $vr0, $vr1, 3123; CHECK-NEXT: ret24entry:25 %res = call <8 x i16> @llvm.loongarch.lsx.vsrani.h.w(<8 x i16> %va, <8 x i16> %vb, i32 31)26 ret <8 x i16> %res27}28 29declare <4 x i32> @llvm.loongarch.lsx.vsrani.w.d(<4 x i32>, <4 x i32>, i32)30 31define <4 x i32> @lsx_vsrani_w_d(<4 x i32> %va, <4 x i32> %vb) nounwind {32; CHECK-LABEL: lsx_vsrani_w_d:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vsrani.w.d $vr0, $vr1, 6335; CHECK-NEXT: ret36entry:37 %res = call <4 x i32> @llvm.loongarch.lsx.vsrani.w.d(<4 x i32> %va, <4 x i32> %vb, i32 63)38 ret <4 x i32> %res39}40 41declare <2 x i64> @llvm.loongarch.lsx.vsrani.d.q(<2 x i64>, <2 x i64>, i32)42 43define <2 x i64> @lsx_vsrani_d_q(<2 x i64> %va, <2 x i64> %vb) nounwind {44; CHECK-LABEL: lsx_vsrani_d_q:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vsrani.d.q $vr0, $vr1, 12747; CHECK-NEXT: ret48entry:49 %res = call <2 x i64> @llvm.loongarch.lsx.vsrani.d.q(<2 x i64> %va, <2 x i64> %vb, i32 127)50 ret <2 x i64> %res51}52