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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5declare <16 x i8> @llvm.loongarch.lsx.vssrlrn.b.h(<8 x i16>, <8 x i16>)6 7define <16 x i8> @lsx_vssrlrn_b_h(<8 x i16> %va, <8 x i16> %vb) nounwind {8; CHECK-LABEL: lsx_vssrlrn_b_h:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vssrlrn.b.h $vr0, $vr0, $vr111; CHECK-NEXT: ret12entry:13 %res = call <16 x i8> @llvm.loongarch.lsx.vssrlrn.b.h(<8 x i16> %va, <8 x i16> %vb)14 ret <16 x i8> %res15}16 17declare <8 x i16> @llvm.loongarch.lsx.vssrlrn.h.w(<4 x i32>, <4 x i32>)18 19define <8 x i16> @lsx_vssrlrn_h_w(<4 x i32> %va, <4 x i32> %vb) nounwind {20; CHECK-LABEL: lsx_vssrlrn_h_w:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: vssrlrn.h.w $vr0, $vr0, $vr123; CHECK-NEXT: ret24entry:25 %res = call <8 x i16> @llvm.loongarch.lsx.vssrlrn.h.w(<4 x i32> %va, <4 x i32> %vb)26 ret <8 x i16> %res27}28 29declare <4 x i32> @llvm.loongarch.lsx.vssrlrn.w.d(<2 x i64>, <2 x i64>)30 31define <4 x i32> @lsx_vssrlrn_w_d(<2 x i64> %va, <2 x i64> %vb) nounwind {32; CHECK-LABEL: lsx_vssrlrn_w_d:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vssrlrn.w.d $vr0, $vr0, $vr135; CHECK-NEXT: ret36entry:37 %res = call <4 x i32> @llvm.loongarch.lsx.vssrlrn.w.d(<2 x i64> %va, <2 x i64> %vb)38 ret <4 x i32> %res39}40 41declare <16 x i8> @llvm.loongarch.lsx.vssrlrn.bu.h(<8 x i16>, <8 x i16>)42 43define <16 x i8> @lsx_vssrlrn_bu_h(<8 x i16> %va, <8 x i16> %vb) nounwind {44; CHECK-LABEL: lsx_vssrlrn_bu_h:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vssrlrn.bu.h $vr0, $vr0, $vr147; CHECK-NEXT: ret48entry:49 %res = call <16 x i8> @llvm.loongarch.lsx.vssrlrn.bu.h(<8 x i16> %va, <8 x i16> %vb)50 ret <16 x i8> %res51}52 53declare <8 x i16> @llvm.loongarch.lsx.vssrlrn.hu.w(<4 x i32>, <4 x i32>)54 55define <8 x i16> @lsx_vssrlrn_hu_w(<4 x i32> %va, <4 x i32> %vb) nounwind {56; CHECK-LABEL: lsx_vssrlrn_hu_w:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vssrlrn.hu.w $vr0, $vr0, $vr159; CHECK-NEXT: ret60entry:61 %res = call <8 x i16> @llvm.loongarch.lsx.vssrlrn.hu.w(<4 x i32> %va, <4 x i32> %vb)62 ret <8 x i16> %res63}64 65declare <4 x i32> @llvm.loongarch.lsx.vssrlrn.wu.d(<2 x i64>, <2 x i64>)66 67define <4 x i32> @lsx_vssrlrn_wu_d(<2 x i64> %va, <2 x i64> %vb) nounwind {68; CHECK-LABEL: lsx_vssrlrn_wu_d:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vssrlrn.wu.d $vr0, $vr0, $vr171; CHECK-NEXT: ret72entry:73 %res = call <4 x i32> @llvm.loongarch.lsx.vssrlrn.wu.d(<2 x i64> %va, <2 x i64> %vb)74 ret <4 x i32> %res75}76